Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

6 files changed, 107 insertions, 53 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index faddee9..b2cc2fe 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -68,6 +68,31 @@
 		       "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);	\
 	} while (0)
 
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+static void update_rdcc(void)
+{
+	u32 val;
+
+	/*
+	 * Complete RDSS configuration as mentioned on page 7 of the AMCC
+	 * PowerPC440SP/SPe DDR2 application note:
+	 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+	 *
+	 * Or item #10 "10. Complete RDSS configuration" in chapter
+	 * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
+	 * manual.
+	 */
+	mfsdram(SDRAM_RTSR, val);
+	if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
+		mfsdram(SDRAM_RDCC, val);
+		if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
+			val += 0x40000000;
+			mtsdram(SDRAM_RDCC, val);
+		}
+	}
+}
+#endif
+
 #if defined(CONFIG_440)
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
@@ -620,6 +645,12 @@ phys_size_t initdram(int board_type)
 #else
 	program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 #endif
+	/*
+	 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
+	 * PowerPC440SP/SPe DDR2 application note:
+	 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+	 */
+	update_rdcc();
 
 #ifdef CONFIG_DDR_ECC
 	/*------------------------------------------------------------------
@@ -2692,20 +2723,6 @@ calibration_loop:
 	blank_string(strlen(str));
 #endif /* CONFIG_DDR_RQDC_FIXED */
 
-	/*
-	 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
-	 * PowerPC440SP/SPe DDR2 application note:
-	 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
-	 */
-	mfsdram(SDRAM_RTSR, val);
-	if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
-		mfsdram(SDRAM_RDCC, val);
-		if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
-			val += 0x40000000;
-			mtsdram(SDRAM_RDCC, val);
-		}
-	}
-
 	mfsdram(SDRAM_DLCR, val);
 	debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
 	mfsdram(SDRAM_RQDC, val);
@@ -3007,6 +3024,13 @@ phys_size_t initdram(int board_type)
 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
+	/*
+	 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
+	 * PowerPC440SP/SPe DDR2 application note:
+	 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+	 */
+	update_rdcc();
+
 #if defined(CONFIG_DDR_ECC)
 	do_program_ecc(0);
 #endif /* defined(CONFIG_DDR_ECC) */
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index aed0ed7..0f69ef9 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -83,11 +83,6 @@ struct ddrautocal {
 	u32 flags;
 };
 
-struct sdram_timing {
-	u32 wrdtr;
-	u32 clktr;
-};
-
 struct sdram_timing_clks {
 	u32 wrdtr;
 	u32 clktr;
@@ -145,11 +140,12 @@ void
 spd_ddr_init_hang(void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 #endif /* defined(CONFIG_SPD_EEPROM) */
 
-ulong __ddr_scan_option(ulong default_val)
+struct sdram_timing *__ddr_scan_option(struct sdram_timing *default_val)
 {
 	return default_val;
 }
-ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option")));
+struct sdram_timing *ddr_scan_option(struct sdram_timing *)
+	__attribute__((weak, alias("__ddr_scan_option")));
 
 u32 __ddr_rdss_opt(u32 default_val)
 {
@@ -931,7 +927,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
  * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value
  * pairs via a board defined ddr_scan_option() function.
  */
-struct sdram_timing full_scan_options[] = {
+static struct sdram_timing full_scan_options[] = {
 	{0, 0}, {0, 1}, {0, 2}, {0, 3},
 	{1, 0}, {1, 1}, {1, 2}, {1, 3},
 	{2, 0}, {2, 1}, {2, 2}, {2, 3},
@@ -970,10 +966,7 @@ u32 DQS_autocalibration(void)
 
 	memset(&tcal, 0, sizeof(tcal));
 
-	ddr_scan_option((ulong)full_scan_options);
-
-	scan_list =
-	      (struct sdram_timing *)ddr_scan_option((ulong)full_scan_options);
+	scan_list = ddr_scan_option(full_scan_options);
 
 	mfsdram(SDRAM_MCOPT1, val);
 	if ((val & SDRAM_MCOPT1_MCHK_CHK_REP) == SDRAM_MCOPT1_MCHK_CHK_REP)
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
index eed4534..bfba952 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
@@ -476,7 +476,9 @@ void pci_init_board(void)
  *-----------------------------------------------------------------------------*/
 #if defined(CONFIG_440)
 
+#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
 static struct pci_controller ppc440_hose = {0};
+#endif
 
 /*
  * This routine is called to determine if a pci scan should be
@@ -704,6 +706,7 @@ void pci_master_init(struct pci_controller *hose)
 	__attribute__((weak, alias("__pci_master_init")));
 #endif /* CONFIG_SYS_PCI_MASTER_INIT */
 
+#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
 int pci_440_init (struct pci_controller *hose)
 {
 	int reg_num = 0;
@@ -845,12 +848,19 @@ int pci_440_init (struct pci_controller *hose)
 	}
 	return hose->last_busno;
 }
+#endif
 
 void pci_init_board(void)
 {
-	int busno;
+	int busno = 0;
 
+	/*
+	 * Only init PCI when either master or target functionality
+	 * is selected.
+	 */
+#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
 	busno = pci_440_init (&ppc440_hose);
+#endif
 #if (defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
     !defined(CONFIG_PCI_DISABLE_PCIE)
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 8a6e545..c04eede 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -36,6 +36,26 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_PLL_RECONFIG	0
 #endif
 
+#if defined(CONFIG_440EPX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+static void reset_with_rli(void)
+{
+	u32 reg;
+
+	/*
+	 * Set reload inhibit so configuration will persist across
+	 * processor resets
+	 */
+	mfcpr(CPR0_ICFG, reg);
+	reg |= CPR0_ICFG_RLI_MASK;
+	mtcpr(CPR0_ICFG, reg);
+
+	/* Reset processor if configuration changed */
+	__asm__ __volatile__ ("sync; isync");
+	mtspr(SPRN_DBCR0, 0x20000000);
+}
+#endif
+
 void reconfigure_pll(u32 new_cpu_freq)
 {
 #if defined(CONFIG_440EPX)
@@ -166,19 +186,28 @@ void reconfigure_pll(u32 new_cpu_freq)
 		}
 	}
 
-	if (reset_needed) {
+	/* Now reset the CPU if needed */
+	if (reset_needed)
+		reset_with_rli();
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	u32 reg;
+
+	/*
+	 * See "9.2.1.1 Booting with Option E" in the 460EX/GT
+	 * users manual
+	 */
+	mfcpr(CPR0_PLLC, reg);
+	if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
 		/*
-		 * Set reload inhibit so configuration will persist across
-		 * processor resets
+		 * Set engage bit
 		 */
-		mfcpr(CPR0_ICFG, reg);
-		reg &= ~CPR0_ICFG_RLI_MASK;
-		reg |= 1 << 31;
-		mtcpr(CPR0_ICFG, reg);
+		reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG;
+		mtcpr(CPR0_PLLC, reg);
 
-		/* Reset processor if configuration changed */
-		__asm__ __volatile__ ("sync; isync");
-		mtspr(SPRN_DBCR0, 0x20000000);
+		/* Now reset the CPU */
+		reset_with_rli();
 	}
 #endif
 }
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index c739deb..5296dad 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -207,6 +207,10 @@
 		(0x00000000)
 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
 
+#if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
+#define CONFIG_SYS_TLB_FOR_BOOT_FLASH	0	/* use TLB 0 as default */
+#endif
+
 #define function_prolog(func_name)	.text; \
 					.align 2; \
 					.globl func_name; \
@@ -1457,34 +1461,21 @@ relocate_code:
 	isync
 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
 	/*
 	 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
 	 * to speed up the boot process. Now this cache needs to be disabled.
 	 */
-	iccci	0,0			/* Invalidate inst cache */
-	dccci	0,0			/* Invalidate data cache, now no longer our stack */
-	sync
-	isync
-
+#if defined(CONFIG_440)
 	/* Clear all potential pending exceptions */
 	mfspr	r1,SPRN_MCSR
 	mtspr	SPRN_MCSR,r1
-#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
 	addi	r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH	/* Use defined TLB */
-#else
-	addi	r1,r0,0x0000		/* Default TLB entry is #0 */
-#endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
 	tlbre	r0,r1,0x0002		/* Read contents */
 	ori	r0,r0,0x0c00		/* Or in the inhibit, write through bit */
 	tlbwe	r0,r1,0x0002		/* Save it out */
 	sync
 	isync
-#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
+#endif /* defined(CONFIG_440) */
 	mr	r1,  r3		/* Set new stack pointer		*/
 	mr	r9,  r4		/* Save copy of Init Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 92be514..d9506e2 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -344,6 +344,9 @@
 #define SDRAM_RXBAS_SDSZ_2048		SDRAM_RXBAS_SDSZ_2048MB
 #define SDRAM_RXBAS_SDSZ_4096		SDRAM_RXBAS_SDSZ_4096MB
 #define SDRAM_RXBAS_SDSZ_8192		SDRAM_RXBAS_SDSZ_8192MB
+#endif /* CONFIG_405EX */
+
+/* The mode definitions are the same for all PPC4xx variants */
 #define SDRAM_RXBAS_SDAM_MODE0		PPC_REG_VAL(23, 0x0)
 #define SDRAM_RXBAS_SDAM_MODE1		PPC_REG_VAL(23, 0x1)
 #define SDRAM_RXBAS_SDAM_MODE2		PPC_REG_VAL(23, 0x2)
@@ -356,7 +359,6 @@
 #define SDRAM_RXBAS_SDAM_MODE9		PPC_REG_VAL(23, 0x9)
 #define SDRAM_RXBAS_SDBE_DISABLE	PPC_REG_VAL(31, 0x0)
 #define SDRAM_RXBAS_SDBE_ENABLE		PPC_REG_VAL(31, 0x1)
-#endif /* CONFIG_405EX */
 
 /*
  * Memory controller registers
@@ -1394,6 +1396,11 @@
 #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
 
 #ifndef __ASSEMBLY__
+struct sdram_timing {
+	u32 wrdtr;
+	u32 clktr;
+};
+
 /*
  * Prototypes
  */