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authorAnton Staaf <robotboy@chromium.org>2011-10-17 16:46:06 -0700
committerWolfgang Denk <wd@denx.de>2011-10-23 20:50:42 +0200
commit0991701a27e7f1de983ff2250dbdb88a7c8c60ec (patch)
tree5f8c01502bc1e73e248f2393ca29cbec83429324 /arch
parent6fa6035ff2ac62258736ee9365c4b3135a68f4c3 (diff)
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powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/cache.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 53e8d05..e6b8f69 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -21,6 +21,12 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
+/*
* For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
*/
#ifndef CONFIG_SYS_CACHELINE_SIZE