diff options
| author | Ye.Li <B37916@freescale.com> | 2015-03-23 04:56:48 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2015-03-23 22:30:33 +0800 |
| commit | aa8a38edb67d4d1375d10bee9bf46557369fb5c4 (patch) | |
| tree | f1bf62dfc3f7a1433391bc5cbd6640234a5f7581 /arch | |
| parent | ccf3b130d71cf3dd9a97d3bb424931bf6bd7e8c0 (diff) | |
| download | u-boot-imx-aa8a38edb67d4d1375d10bee9bf46557369fb5c4.zip u-boot-imx-aa8a38edb67d4d1375d10bee9bf46557369fb5c4.tar.gz u-boot-imx-aa8a38edb67d4d1375d10bee9bf46557369fb5c4.tar.bz2 | |
MLK-10448-2 mx6: L2cache: Enable the double line fill for i.MX6DQP
Since i.MX6DQP has fixed the L2 cache issue, enable the double line
fill feature to provide better performance.
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 3545d04..c5e2690 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -1068,6 +1068,9 @@ void v7_outer_cache_enable(void) #ifndef CONFIG_MX6Q val |= 0x40800000; +#else + if (is_mx6dqp()) + val |= 0x40800000; #endif writel(val, &pl310->pl310_prefetch_ctrl); |