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authorpekon gupta <pekon@ti.com>2013-11-19 11:02:15 +0530
committerScott Wood <scottwood@freescale.com>2014-03-03 20:09:03 -0600
commitf5f1f614bda83fae868d5634f86e0098162ceb3b (patch)
tree2ff7fa042001df8660f8245c2fb3efc108694613 /arch
parenteeb72e67619b98d2502fe634a3a5d9953de92ad0 (diff)
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mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes
chip->ecc.hwctl() is used for preparing the H/W controller before read/write NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.) Though all ECC schemes in OMAP NAND driver use GPMC controller for generating ECC syndrome (for both Read/Write accesses). But but in current code HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this. This patch (1) removes omap_hwecc_init() and omap_hwecc_init_bch() as chip->ecc.hwctl will re-initializeGPMC before every read/write call. omap_hwecc_init_bch() -> omap_enable_ecc_bch() (2) merges the GPMC configuration code for all ECC schemes into single omap_enable_hwecc(), thus adding scalability for future ECC schemes. omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc() Signed-off-by: Pekon Gupta <pekon@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/omap_gpmc.h7
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h
index d4143ec..6ce5e65 100644
--- a/arch/arm/include/asm/omap_gpmc.h
+++ b/arch/arm/include/asm/omap_gpmc.h
@@ -14,13 +14,6 @@
#define GPMC_BUF_EMPTY 0
#define GPMC_BUF_FULL 1
-#define ECCCLEAR (0x1 << 8)
-#define ECCRESULTREG1 (0x1 << 0)
-#define ECCSIZE512BYTE 0xFF
-#define ECCSIZE1 (ECCSIZE512BYTE << 22)
-#define ECCSIZE0 (ECCSIZE512BYTE << 12)
-#define ECCSIZE0SEL (0x000 << 0)
-
/* Generic ECC Layouts */
/* Large Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT