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authorSughosh Ganu <urwithsughosh@gmail.com>2012-02-02 00:44:38 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-02-12 10:11:33 +0100
commitda104e04ecc30b90fdc121737f220f0d9c252196 (patch)
treee86b6dccc5a566b6ac4abe7e3019fd3fb1bd2c48 /arch
parent27b66622b51f350ce6c143f82d104860ee887f5c (diff)
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arm, arm926ejs: Flush the data cache before disabling it
The current implementation invalidates the data cache before turning it off and causes problems on the hawkboard. See the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html According to the ARM926EJ-S Technical Reference Manual, the cache should be flushed instead. Also fix the comments to match code. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> Rebased and corrected commit message. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/arm926ejs/start.S12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index bb4d00b..b39ed8a 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -358,14 +358,18 @@ _dynsym_start_ofs:
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
/*
- * flush v4 I/D caches
+ * flush D cache before disabling it
*/
mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+flush_dcache:
+ mrc p15, 0, r15, c7, c10, 3
+ bne flush_dcache
+
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
/*
- * disable MMU stuff and caches
+ * disable MMU and D cache, and enable I cache
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */