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authorFabio Estevam <fabio.estevam@freescale.com>2013-12-03 18:26:13 -0200
committerStefano Babic <sbabic@denx.de>2013-12-17 18:38:42 +0100
commit89cfd0f5757413093ad179478b80367d7bd34ecc (patch)
tree9d046959fc79a25c3d6fc3172854027bc8a72320 /arch
parent502a710f5b54bbb966db4c4516abf5d82f46dd47 (diff)
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mx6: clock: Fix the calculation of PLL_ENET frequency
According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 873d9d0..20c7e70 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -94,7 +94,7 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
div = __raw_readl(&imx_ccm->analog_pll_enet);
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
- return (div == 3 ? 125000000 : 25000000 * (div << 1));
+ return 25000000 * (div + (div >> 1) + 1);
default:
return 0;
}