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authorMark Marshall <mark.marshall@omicron.at>2012-09-09 23:06:03 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 03:04:27 -0500
commit320d53da605d67b9d95622c5c6bfd5ac2c17ed58 (patch)
tree6e49a326f648a59146039ba6b3c111d40a795b8a /arch
parent168e5bc4095177764edaff306c9d4674a6f7f5e6 (diff)
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powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.
We should only write TSR_WIS to the SPRN_TSR register in reset_85xx_watchdog. The old code would cause the timer interrupt to be acknowledged when the watchdog was reset, and we would then get no more timer interrupts. This bug would affect all mpc85xx boards that have the watchdog enabled. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 5ddb294..a5048a1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -270,10 +270,7 @@ reset_85xx_watchdog(void)
/*
* Clear TSR(WIS) bit by writing 1
*/
- unsigned long val;
- val = mfspr(SPRN_TSR);
- val |= TSR_WIS;
- mtspr(SPRN_TSR, val);
+ mtspr(SPRN_TSR, TSR_WIS);
}
#endif /* CONFIG_WATCHDOG */