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authorFabio Estevam <fabio.estevam@freescale.com>2013-05-05 16:11:59 +0000
committerStefano Babic <sbabic@denx.de>2013-05-06 09:55:52 +0200
commit286a88cf34bcfec4a1051b5ee3553277e6c31e2e (patch)
tree59ad5d5e2f52b2afc05a4788756d56a4f9e1f9bf /arch
parent0b323439a52daca171cf107a8f479a3ce18d1d3a (diff)
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mxs: Explain why some mx23 DDR registers are not configured
Put an explanation in the source code as to why some DDR registers do not need to be configured. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 4ed197b..3902406 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -127,6 +127,15 @@ static void initialize_dram_values(void)
mxs_adjust_memory_params(dram_vals);
+ /*
+ * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
+ * per FSL bootlets code.
+ *
+ * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
+ * "reserved".
+ * HW_DRAM_CTL8 is setup as the last element.
+ * So skip the initialization of these HW_DRAM_CTL registers.
+ */
for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
if (i == 8 || i == 27 || i == 28 || i == 35)
continue;