summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorSimon Glass <sjg@chromium.org>2012-04-02 13:18:51 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-05-15 08:31:37 +0200
commit1d5dba604c93bc2916cbd30c239bc8d237f12073 (patch)
tree75d19f582f29c59c88d7f72e35196ec68be7f7e9 /arch
parentd515362d4d6f83be818f71d37a4600041a520ab5 (diff)
downloadu-boot-imx-1d5dba604c93bc2916cbd30c239bc8d237f12073.zip
u-boot-imx-1d5dba604c93bc2916cbd30c239bc8d237f12073.tar.gz
u-boot-imx-1d5dba604c93bc2916cbd30c239bc8d237f12073.tar.bz2
tegra: Add header file for APB_MISC register
Add a basic header file for this register, to be filled in as needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-tegra2/apb_misc.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra2/apb_misc.h b/arch/arm/include/asm/arch-tegra2/apb_misc.h
new file mode 100644
index 0000000..eb69d18
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/apb_misc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _GP_PADCTRL_H_
+#define _GP_PADCTRL_H_
+
+/* APB_MISC_PP registers */
+struct apb_misc_pp_ctlr {
+ u32 reserved0[2];
+ u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
+};
+
+/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
+#define RAM_CODE_SHIFT 4
+#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT)
+
+#endif