Merge branch 'master' of git://git.denx.de/u-boot-arm

45 files changed, 2716 insertions, 2136 deletions

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 6923f6d..21c1e33 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -33,11 +33,6 @@ STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif
 
-ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
-# needed for relocation
-PLATFORM_RELFLAGS += -fPIC
-endif
-
 ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
 PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC
 endif
@@ -72,3 +67,10 @@ PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
 endif
 endif
 LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
+# needed for relocation
+ifndef CONFIG_NAND_SPL
+PLATFORM_LDFLAGS += -pie
+endif
+endif
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 5008ac6..29ed065 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -89,48 +89,35 @@ _end_vect:
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
  */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
-
-.globl _bss_end
-_bss_end:
-	.word _end
-
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _datarel_start
-_datarel_start:
-	.word __datarel_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
 
-.globl _datarelrolocal_start
-_datarelrolocal_start:
-	.word __datarelrolocal_start
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word _end - _start
 
-.globl _datarellocal_start
-_datarellocal_start:
-	.word __datarellocal_start
+.globl _datarel_start_ofs
+_datarel_start_ofs:
+	.word __datarel_start - _start
 
-.globl _datarelro_start
-_datarelro_start:
-	.word __datarelro_start
+.globl _datarelrolocal_start_ofs
+_datarelrolocal_start_ofs:
+	.word __datarelrolocal_start - _start
 
-.globl _got_start
-_got_start:
-	.word __got_start
+.globl _datarellocal_start_ofs
+_datarellocal_start_ofs:
+	.word __datarellocal_start - _start
 
-.globl _got_end
-_got_end:
-	.word __got_end
-#endif
+.globl _datarelro_start_ofs
+_datarelro_start_ofs:
+	.word __datarelro_start - _start
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -225,9 +212,8 @@ stack_setup:
 
 	adr	r0, _start
 	ldr	r2, _TEXT_BASE
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot	    */
-	add	r2, r0, r2		/* r2 <- source end address	    */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
 	cmp	r0, r6
 	beq	clear_bss
 
@@ -239,36 +225,54 @@ copy_loop:
 	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
-	/* fix got entries */
-	ldr	r1, _TEXT_BASE
-	mov	r0, r7			/* reloc addr */
-	ldr	r2, _got_start		/* addr in Flash */
-	ldr	r3, _got_end		/* addr in Flash */
-	sub	r3, r3, r1
-	add	r3, r3, r0
-	sub	r2, r2, r1
-	add	r2, r2, r0
-
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r7, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
 fixloop:
-	ldr	r4, [r2]
-	sub	r4, r4, r1
-	add	r4, r4, r0
-	str	r4, [r2]
-	add	r2, r2, #4
+	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r8, r1, #0xff
+	cmp	r8, #23		/* relative fixup? */
+	beq	fixrel
+	cmp	r8, #2		/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r9			/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
-	bne	fixloop
+	ble	fixloop
 #endif
 #endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start
-	ldr	r1, _bss_end
+	ldr	r0, _bss_start_ofs
+	ldr	r1, _bss_end_ofs
 	ldr	r3, _TEXT_BASE		/* Text base */
 	mov	r4, r7			/* reloc addr */
-	sub	r0, r0, r3
 	add	r0, r0, r4
-	sub	r1, r1, r3
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
@@ -283,24 +287,34 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
  * initialization, now running from RAM.
  */
 #ifdef CONFIG_NAND_SPL
-	ldr     pc, _nand_boot
-
-_nand_boot: .word nand_boot
+	ldr     r0, _nand_boot_ofs
+	adr	r1, _start
+	add	pc, r0, r1
+_nand_boot_ofs
+	: .word nand_boot - _start
 #else
 jump_2_ram:
-	ldr	r0, _TEXT_BASE
-	ldr	r2, _board_init_r
-	sub	r2, r2, r0
-	add	r2, r2, r7	/* position from board_init_r in RAM */
+	ldr	r0, _board_init_r_ofs
+	adr	r1, _start
+	add	r0, r0, r1
+	add	lr, r0, r9
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r7		/* dest_addr */
 	/* jump to it ... */
-	mov	lr, r2
 	mov	pc, lr
 
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+	.word board_init_r - _start
 #endif
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 /*
  * the actual reset code
@@ -375,8 +389,11 @@ stack_setup:
 	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
 
 clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment	    */
-	ldr	r1, _bss_end		/* stop here			    */
+	adr	r2, _start
+	ldr	r0, _bss_start_ofs	/* find start of bss segment        */
+	add	r0, r0, r2
+	ldr	r1, _bss_end_ofs	/* stop here                        */
+	add	r1, r1, r2
 	mov	r2, #0x00000000		/* clear			    */
 
 #ifndef CONFIG_PRELOADER
@@ -386,15 +403,19 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	bne	clbss_l
 #endif
 
-	ldr	pc, _start_armboot
+	ldr	r0, _start_armboot_ofs
+	adr	r1, _start
+	add	r0, r0, r1
+	ldr	pc, r0
 
+_start_armboot_ofs:
 #ifdef CONFIG_NAND_SPL
-_start_armboot: .word nand_boot
+	.word nand_boot - _start
 #else
 #ifdef CONFIG_ONENAND_IPL
-_start_armboot: .word start_oneboot
+	.word start_oneboot - _start
 #else
-_start_armboot: .word start_armboot
+	.word start_armboot - _start
 #endif /* CONFIG_ONENAND_IPL */
 #endif /* CONFIG_NAND_SPL */
 
@@ -487,7 +508,7 @@ cpu_init_crit:
 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
 #else
-	ldr	r2, _armboot_start
+	adr	r2, _start
 	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
 	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ set base 2 words into abort stack
 #endif
@@ -524,8 +545,8 @@ cpu_init_crit:
 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
 #else
-	ldr	r13, _armboot_start		@ setup our mode stack (enter in banked mode)
-	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
+	adr	r13, _start			@ setup our mode stack (enter in banked mode)
+	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
 	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
 #endif
 
diff --git a/arch/arm/cpu/arm1136/u-boot.lds b/arch/arm/cpu/arm1136/u-boot.lds
index 1db4b49..31f43f0 100644
--- a/arch/arm/cpu/arm1136/u-boot.lds
+++ b/arch/arm/cpu/arm1136/u-boot.lds
@@ -59,11 +59,14 @@ SECTIONS
 		*(.data.rel.ro)
 	}
 
-	__got_start = .;
 	. = ALIGN(4);
-	.got : { *(.got) }
+	__rel_dyn_start = .;
+	.rel.dyn : { *(.rel.dyn) }
+	__rel_dyn_end = .;
+
+	__dynsym_start = .;
+	.dynsym : { *(.dynsym) }
 
-	__got_end = .;
 	. = .;
 	__u_boot_cmd_start = .;
 	.u_boot_cmd : { *(.u_boot_cmd) }
@@ -73,4 +76,10 @@ SECTIONS
 	__bss_start = .;
 	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
 	_end = .;
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
 }
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
index ecf91f5..7a10a77 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -11,47 +11,46 @@
  * (at your option) any later version.
  */
 
-#include <config.h>
+#include <common.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/io.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 
-static unsigned long cpu_clk_rate_hz;
-static unsigned long main_clk_rate_hz;
-static unsigned long mck_rate_hz;
-static unsigned long plla_rate_hz;
-static unsigned long pllb_rate_hz;
-static u32 at91_pllb_usb_init;
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
 unsigned long get_cpu_clk_rate(void)
 {
-	return cpu_clk_rate_hz;
+	return gd->cpu_clk_rate_hz;
 }
 
 unsigned long get_main_clk_rate(void)
 {
-	return main_clk_rate_hz;
+	return gd->main_clk_rate_hz;
 }
 
 unsigned long get_mck_clk_rate(void)
 {
-	return mck_rate_hz;
+	return gd->mck_rate_hz;
 }
 
 unsigned long get_plla_clk_rate(void)
 {
-	return plla_rate_hz;
+	return gd->plla_rate_hz;
 }
 
 unsigned long get_pllb_clk_rate(void)
 {
-	return pllb_rate_hz;
+	return gd->pllb_rate_hz;
 }
 
 u32 get_pllb_init(void)
 {
-	return at91_pllb_usb_init;
+	return gd->at91_pllb_usb_init;
 }
 
 static unsigned long at91_css_to_rate(unsigned long css)
@@ -60,11 +59,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
 	case AT91_PMC_MCKR_CSS_SLOW:
 		return AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
-		return main_clk_rate_hz;
+		return gd->main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
-		return plla_rate_hz;
+		return gd->plla_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLB:
-		return pllb_rate_hz;
+		return gd->pllb_rate_hz;
 	}
 
 	return 0;
@@ -163,10 +162,10 @@ int at91_clock_init(unsigned long main_clock)
 		main_clock = tmp * (AT91_SLOW_CLOCK / 16);
 	}
 #endif
-	main_clk_rate_hz = main_clock;
+	gd->main_clk_rate_hz = main_clock;
 
 	/* report if PLLA is more than mildly overclocked */
-	plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+	gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 
 #ifdef CONFIG_USB_ATMEL
 	/*
@@ -175,9 +174,9 @@ int at91_clock_init(unsigned long main_clock)
 	 *
 	 * REVISIT:  assumes MCK doesn't derive from PLLB!
 	 */
-	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+	gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
 			     AT91_PMC_PLLBR_USBDIV_2;
-	pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
+	gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
 #endif
 
 	/*
@@ -187,30 +186,30 @@ int at91_clock_init(unsigned long main_clock)
 	mckr = readl(&pmc->mckr);
 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 	/* plla divisor by 2 */
-	plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+	gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 #endif
-	mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = mck_rate_hz;
+	gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->mck_rate_hz;
 
 	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
 #if defined(CONFIG_AT91RM9200)
 	/* mdiv */
-	mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+	gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #elif defined(CONFIG_AT91SAM9G20)
 	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
-	mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
 		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
 	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
 		freq /= 2;			/* processor clock division */
 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-	mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
 		(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
 		? freq / 3
 		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #else
-	mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+	gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #endif
-	cpu_clk_rate_hz = freq;
+	gd->cpu_clk_rate_hz = freq;
 
 	return 0;
 }
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c
index 8efc34b..82b8d7e 100644
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -30,55 +30,63 @@
 #include <asm/arch/io.h>
 #include <div64.h>
 
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  * setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
  */
-#define TIMER_LOAD_VAL	0xfffff
 
-static ulong timestamp;
-static ulong lastinc;
-static ulong timer_freq;
+#define TIMER_LOAD_VAL	0xfffff
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, timer_freq);
+	do_div(tick, gd->timer_rate_hz);
 
 	return tick;
 }
 
 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-	usec *= timer_freq;
+	usec *= gd->timer_rate_hz;
 	do_div(usec, 1000000);
 
 	return usec;
 }
 
-/* nothing really to do with interrupts, just starts up a counter. */
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
 int timer_init(void)
 {
 	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
 	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-	/*
-	 * Enable PITC Clock
-	 * The clock is already enabled for system controller in boot
-	 */
+
+	/* Enable PITC Clock */
 	writel(1 << AT91_ID_SYS, &pmc->pcer);
 
 	/* Enable PITC */
 	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
 
-	reset_timer_masked();
-
-	timer_freq = get_mck_clk_rate() >> 4;
+	gd->timer_rate_hz = gd->mck_rate_hz / 16;
+	gd->tbu = gd->tbl = 0;
 
 	return 0;
 }
 
 /*
- * timer without interrupts
+ * Get the current 64 bit timer tick count
  */
 unsigned long long get_ticks(void)
 {
@@ -86,28 +94,11 @@ unsigned long long get_ticks(void)
 
 	ulong now = readl(&pit->piir);
 
-	if (now >= lastinc)	/* normal mode (non roll) */
-		/* move stamp forward with absolut diff ticks */
-		timestamp += (now - lastinc);
-	else			/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	lastinc = now;
-	return timestamp;
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-
-	/* capture current incrementer value time */
-	lastinc = readl(&pit->piir);
-	timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
-	return tick_to_time(get_ticks());
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->tbl)
+		gd->tbu++;
+	gd->tbl = now;
+	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
 }
 
 void __udelay(unsigned long usec)
@@ -119,24 +110,32 @@ void __udelay(unsigned long usec)
 	tmp = get_ticks() + tmo;	/* get current timestamp */
 
 	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
+		;
 }
 
+/*
+ * reset_timer() and get_timer(base) are a pair of functions that are used by
+ * some timeout/sleep mechanisms in u-boot.
+ *
+ * reset_timer() marks the current time as epoch and
+ * get_timer(base) works relative to that epoch.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
 void reset_timer(void)
 {
-	reset_timer_masked();
+	gd->timer_reset_value = get_ticks();
 }
 
 ulong get_timer(ulong base)
 {
-	return get_timer_masked () - base;
+	return tick_to_time(get_ticks() - gd->timer_reset_value) - base;
 }
 
 /*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
+ * Return the number of timer ticks per second.
  */
 ulong get_tbclk(void)
 {
-	return timer_freq;
+	return gd->timer_rate_hz;
 }
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 8cbe3e7..863de3b 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -10,6 +10,7 @@
  *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
  *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
  *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *  Copyright (c) 2010	Albert Aribaud <albert.aribaud@free.fr>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -118,22 +119,19 @@ _fiq:
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
  */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
 
-.globl _bss_end
-_bss_end:
-	.word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -153,30 +151,6 @@ FIQ_STACK_START:
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 
-.globl _datarel_start
-_datarel_start:
-	.word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
-	.word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
-	.word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
-	.word __datarelro_start
-
-.globl _got_start
-_got_start:
-	.word __got_start
-
-.globl _got_end
-_got_end:
-	.word __got_end
-
 /*
  * the actual reset code
  */
@@ -226,9 +200,8 @@ stack_setup:
 
 	adr	r0, _start
 	ldr	r2, _TEXT_BASE
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot	    */
-	add	r2, r0, r2		/* r2 <- source end address	    */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
 	cmp	r0, r6
 	beq	clear_bss
 
@@ -240,36 +213,54 @@ copy_loop:
 	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
-	/* fix got entries */
-	ldr	r1, _TEXT_BASE		/* Text base */
-	mov	r0, r7			/* reloc addr */
-	ldr	r2, _got_start		/* addr in Flash */
-	ldr	r3, _got_end		/* addr in Flash */
-	sub	r3, r3, r1
-	add	r3, r3, r0
-	sub	r2, r2, r1
-	add	r2, r2, r0
-
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r7, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
 fixloop:
-	ldr	r4, [r2]
-	sub	r4, r4, r1
-	add	r4, r4, r0
-	str	r4, [r2]
-	add	r2, r2, #4
+	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r8, r1, #0xff
+	cmp	r8, #23		/* relative fixup? */
+	beq	fixrel
+	cmp	r8, #2		/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r9			/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
 #endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start
-	ldr	r1, _bss_end
+	ldr	r0, _bss_start_ofs
+	ldr	r1, _bss_end_ofs
 	ldr	r3, _TEXT_BASE		/* Text base */
 	mov	r4, r7			/* reloc addr */
-	sub	r0, r0, r3
 	add	r0, r0, r4
-	sub	r1, r1, r3
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
@@ -287,24 +278,33 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
  * initialization, now running from RAM.
  */
 #ifdef CONFIG_NAND_SPL
-	ldr     pc, _nand_boot
+	ldr     r0, _nand_boot_ofs
+	mov	pc, r0
 
-_nand_boot: .word nand_boot
+_nand_boot_ofs:
+	.word nand_boot
 #else
-	ldr	r0, _TEXT_BASE
-	ldr	r2, _board_init_r
-	sub	r2, r2, r0
-	add	r2, r2, r7	/* position from board_init_r in RAM */
+	ldr	r0, _board_init_r_ofs
+	adr	r1, _start
+	add	r0, r0, r1
+	add	lr, r0, r9
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r7		/* dest_addr */
 	/* jump to it ... */
-	mov	lr, r2
 	mov	pc, lr
 
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+	.word board_init_r - _start
 #endif
 
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 /*
  * the actual reset code
@@ -333,10 +333,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
 	cmp     r0, r1                  /* don't reloc during debug         */
 	beq     stack_setup
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
+	ldr	r3, _bss_start_ofs	/* r3 <- _bss_start - _start	    */
+	add	r2, r0, r3		/* r2 <- source end address         */
 
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
@@ -360,8 +358,11 @@ stack_setup:
 	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
 
 clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
+	adr	r2, _start
+	ldr	r0, _bss_start_ofs	/* find start of bss segment        */
+	add	r0, r0, r2
+	ldr	r1, _bss_end_ofs	/* stop here                        */
+	add	r1, r1, r2
 	mov	r2, #0x00000000		/* clear                            */
 
 #ifndef CONFIG_PRELOADER
@@ -374,13 +375,16 @@ clbss_l:str	r2, [r0]		/* clear loop...                    */
 	bl red_LED_on
 #endif /* CONFIG_PRELOADER */
 
-	ldr	pc, _start_armboot
+	ldr	r0, _start_armboot_ofs
+	adr	r1, _start
+	add	r0, r0, r1
+	ldr	pc, r0
 
-_start_armboot:
+_start_armboot_ofs:
 #ifdef CONFIG_NAND_SPL
-	.word nand_boot
+	.word nand_boot - _start
 #else
-	.word start_armboot
+	.word start_armboot - _start
 #endif /* CONFIG_NAND_SPL */
 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 
@@ -469,7 +473,7 @@ cpu_init_crit:
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
+	adr	r2, _start
 	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
 	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 #else
@@ -507,7 +511,7 @@ cpu_init_crit:
 
 	.macro get_bad_stack
 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
+	adr	r13, _start		@ setup our mode stack
 	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
 	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 #else
diff --git a/arch/arm/cpu/arm926ejs/u-boot.lds b/arch/arm/cpu/arm926ejs/u-boot.lds
index 02eb8ca..72f45f8 100644
--- a/arch/arm/cpu/arm926ejs/u-boot.lds
+++ b/arch/arm/cpu/arm926ejs/u-boot.lds
@@ -41,21 +41,19 @@ SECTIONS
 	. = ALIGN(4);
 	.data : {
 		*(.data)
-	__datarel_start = .;
-		*(.data.rel)
-	__datarelrolocal_start = .;
-		*(.data.rel.ro.local)
-	__datarellocal_start = .;
-		*(.data.rel.local)
-	__datarelro_start = .;
-		*(.data.rel.ro)
 	}
 
-	__got_start = .;
 	. = ALIGN(4);
-	.got : { *(.got) }
 
-	__got_end = .;
+	__rel_dyn_start = .;
+	.rel.dyn : { *(.rel.dyn) }
+	__rel_dyn_end = .;
+
+	__dynsym_start = .;
+	.dynsym : { *(.dynsym) }
+
+	. = ALIGN(4);
+
 	. = .;
 	__u_boot_cmd_start = .;
 	.u_boot_cmd : { *(.u_boot_cmd) }
@@ -65,4 +63,10 @@ SECTIONS
 	__bss_start = .;
 	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
 	_end = .;
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
 }
diff --git a/arch/arm/cpu/armv7/mx51/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index 7cfaa2c..7cfaa2c 100644
--- a/arch/arm/cpu/armv7/mx51/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
diff --git a/arch/arm/cpu/armv7/mx51/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index a27227d..00f649c 100644
--- a/arch/arm/cpu/armv7/mx51/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -71,7 +71,7 @@ u32 get_mcu_main_clk(void)
 
 	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
 		MXC_CCM_CACRR_ARM_PODF_OFFSET;
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
 	return freq / (reg + 1);
 }
 
@@ -84,14 +84,14 @@ static u32 get_periph_clk(void)
 
 	reg = __raw_readl(&mxc_ccm->cbcdr);
 	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
-		return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
+		return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
 	reg = __raw_readl(&mxc_ccm->cbcmr);
 	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
 		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
 	case 0:
-		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
 	case 1:
-		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
+		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
 	default:
 		return 0;
 	}
@@ -146,15 +146,15 @@ static u32 get_uart_clk(void)
 		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
 	case 0x0:
 		freq = decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
+				    CONFIG_SYS_MX5_HCLK);
 		break;
 	case 0x1:
 		freq = decode_pll(mxc_plls[PLL2_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
+				    CONFIG_SYS_MX5_HCLK);
 		break;
 	case 0x2:
 		freq = decode_pll(mxc_plls[PLL3_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
+				    CONFIG_SYS_MX5_HCLK);
 		break;
 	default:
 		return 66500000;
@@ -181,7 +181,7 @@ u32 get_lp_apm(void)
 	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
 
 	if (((ccsr >> 9) & 1) == 0)
-		ret_val = CONFIG_MX51_HCLK_FREQ;
+		ret_val = CONFIG_SYS_MX5_HCLK;
 	else
 		ret_val = ((32768 * 1024));
 
@@ -207,17 +207,17 @@ u32 imx_get_cspiclk(void)
 	switch (clk_sel) {
 	case 0:
 		ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
-					CONFIG_MX51_HCLK_FREQ) /
+					CONFIG_SYS_MX5_HCLK) /
 					((pre_pdf + 1) * (pdf + 1));
 		break;
 	case 1:
 		ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
-					CONFIG_MX51_HCLK_FREQ) /
+					CONFIG_SYS_MX5_HCLK) /
 					((pre_pdf + 1) * (pdf + 1));
 		break;
 	case 2:
 		ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
-					CONFIG_MX51_HCLK_FREQ) /
+					CONFIG_SYS_MX5_HCLK) /
 					((pre_pdf + 1) * (pdf + 1));
 		break;
 	default:
@@ -248,7 +248,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return imx_get_cspiclk();
 	case MXC_FEC_CLK:
 		return decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
+				    CONFIG_SYS_MX5_HCLK);
 	default:
 		break;
 	}
@@ -269,16 +269,16 @@ u32 imx_get_fecclk(void)
 /*
  * Dump some core clockes.
  */
-int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	u32 freq;
 
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	printf("mx51 pll1: %dMHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	printf("mx51 pll2: %dMHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	printf("mx51 pll3: %dMHz\n", freq / 1000000);
+	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+	printf("pll1: %dMHz\n", freq / 1000000);
+	freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+	printf("pll2: %dMHz\n", freq / 1000000);
+	freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+	printf("pll3: %dMHz\n", freq / 1000000);
 	printf("ipg clock     : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
 	printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
 
@@ -288,7 +288,7 @@ int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
 /***************************************************/
 
 U_BOOT_CMD(
-	clockinfo,	CONFIG_SYS_MAXARGS,	1,	do_mx51_showclocks,
-	"display mx51 clocks\n",
+	clockinfo,	CONFIG_SYS_MAXARGS,	1,	do_mx5_showclocks,
+	"display clocks\n",
 	""
 );
diff --git a/arch/arm/cpu/armv7/mx51/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c
index 62b2954..e8928d5 100644
--- a/arch/arm/cpu/armv7/mx51/iomux.c
+++ b/arch/arm/cpu/armv7/mx5/iomux.c
@@ -23,7 +23,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
 
diff --git a/arch/arm/cpu/armv7/mx51/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 783c81f..e984870 100644
--- a/arch/arm/cpu/armv7/mx51/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -257,20 +257,6 @@ lowlevel_init:
 	orr r1, r1, #(1 << 23)
 	str r1, [r0, #0x4]
 
-#ifdef ENABLE_IMPRECISE_ABORT
-	mrs r1, spsr		/* save old spsr */
-	mrs r0, cpsr		/* read out the cpsr */
-	bic r0, r0, #0x100	/* clear the A bit */
-	msr spsr, r0		/* update spsr */
-	add lr, pc, #0x8	/* update lr */
-	movs pc, lr		/* update cpsr */
-	nop
-	nop
-	nop
-	nop
-	msr spsr, r1		/* restore old spsr */
-#endif
-
 	init_l2cc
 
 	init_aips
diff --git a/arch/arm/cpu/armv7/mx51/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index f22ebe9..7c7a565 100644
--- a/arch/arm/cpu/armv7/mx51/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -33,28 +33,33 @@
 #include <fsl_esdhc.h>
 #endif
 
+#if defined(CONFIG_MX51)
+#define CPU_TYPE 0x51000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
 u32 get_cpu_rev(void)
 {
-	int reg;
-	int system_rev;
+	int system_rev = CPU_TYPE;
+	int reg = __raw_readl(ROM_SI_REV);
 
-	reg = __raw_readl(ROM_SI_REV);
 	switch (reg) {
 	case 0x02:
-		system_rev = 0x51000 | CHIP_REV_1_1;
+		system_rev |= CHIP_REV_1_1;
 		break;
 	case 0x10:
 		if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
-			system_rev = 0x51000 | CHIP_REV_2_5;
+			system_rev |= CHIP_REV_2_5;
 		else
-			system_rev = 0x51000 | CHIP_REV_2_0;
+			system_rev |= CHIP_REV_2_0;
 		break;
 	case 0x20:
-		system_rev = 0x51000 | CHIP_REV_3_0;
+		system_rev |= CHIP_REV_3_0;
 		break;
 	return system_rev;
 	default:
-		system_rev = 0x51000 | CHIP_REV_1_0;
+		system_rev |= CHIP_REV_1_0;
 		break;
 	}
 	return system_rev;
@@ -67,9 +72,10 @@ int print_cpuinfo(void)
 	u32 cpurev;
 
 	cpurev = get_cpu_rev();
-	printf("CPU:   Freescale i.MX51 family rev%d.%d at %d MHz\n",
-		(cpurev & 0xF0) >> 4,
-		(cpurev & 0x0F) >> 4,
+	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
+		(cpurev & 0xFF000) >> 12,
+		(cpurev & 0x000F0) >> 4,
+		(cpurev & 0x0000F) >> 0,
 		mxc_get_clock(MXC_ARM_CLK) / 1000000);
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/mx51/speed.c b/arch/arm/cpu/armv7/mx5/speed.c
index a444def..a444def 100644
--- a/arch/arm/cpu/armv7/mx51/speed.c
+++ b/arch/arm/cpu/armv7/mx5/speed.c
diff --git a/arch/arm/cpu/armv7/mx51/timer.c b/arch/arm/cpu/armv7/mx5/timer.c
index 110edbf..3044fcf 100644
--- a/arch/arm/cpu/armv7/mx51/timer.c
+++ b/arch/arm/cpu/armv7/mx5/timer.c
@@ -75,18 +75,18 @@ void reset_timer(void)
 void reset_timer_masked(void)
 {
 	ulong val = __raw_readl(&cur_gpt->counter);
-	lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+	lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
 	timestamp = 0;
 }
 
 ulong get_timer_masked(void)
 {
 	ulong val = __raw_readl(&cur_gpt->counter);
-	val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+	val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
 	if (val >= lastinc)
 		timestamp += (val - lastinc);
 	else
-		timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
+		timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
 				- lastinc) + val;
 	lastinc = val;
 	return timestamp;
@@ -106,7 +106,7 @@ void set_timer(ulong t)
 void __udelay(unsigned long usec)
 {
 	unsigned long now, start, tmo;
-	tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
+	tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
 
 	if (!tmo)
 		tmo = 1;
diff --git a/arch/arm/cpu/armv7/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx5/u-boot.lds
index 55d6599..55d6599 100644
--- a/arch/arm/cpu/armv7/mx51/u-boot.lds
+++ b/arch/arm/cpu/armv7/mx5/u-boot.lds
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 26f335a..64c86e9 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -78,13 +78,13 @@ _armboot_start:
 /*
  * These are defined in the board-specific linker script.
  */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
 
-.globl _bss_end
-_bss_end:
-	.word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -104,29 +104,29 @@ FIQ_STACK_START:
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 
-.globl _datarel_start
-_datarel_start:
-	.word __datarel_start
+.globl _datarel_start_ofs
+_datarel_start_ofs:
+	.word __datarel_start - _start
 
-.globl _datarelrolocal_start
-_datarelrolocal_start:
-	.word __datarelrolocal_start
+.globl _datarelrolocal_start_ofs
+_datarelrolocal_start_ofs:
+	.word __datarelrolocal_start - _start
 
-.globl _datarellocal_start
-_datarellocal_start:
-	.word __datarellocal_start
+.globl _datarellocal_start_ofs
+_datarellocal_start_ofs:
+	.word __datarellocal_start - _start
 
-.globl _datarelro_start
-_datarelro_start:
-	.word __datarelro_start
+.globl _datarelro_start_ofs
+_datarelro_start_ofs:
+	.word __datarelro_start - _start
 
-.globl _got_start
-_got_start:
-	.word __got_start
+.globl _got_start_ofs
+_got_start_ofs:
+	.word __got_start - _start
 
-.globl _got_end
-_got_end:
-	.word __got_end
+.globl _got_end_Ofs
+_got_end_ofs:
+	.word __got_end - _start
 
 /*
  * the actual reset code
@@ -198,9 +198,8 @@ stack_setup:
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 	adr	r0, _start
 	ldr	r2, _TEXT_BASE
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot	    */
-	add	r2, r0, r2		/* r2 <- source end address	    */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
 	cmp	r0, r6
 #ifndef CONFIG_PRELOADER
 	beq	jump_2_ram
@@ -213,33 +212,51 @@ copy_loop:
 	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
-	/* fix got entries */
-	ldr	r1, _TEXT_BASE
-	mov	r0, r7			/* reloc addr */
-	ldr	r2, _got_start		/* addr in Flash */
-	ldr	r3, _got_end		/* addr in Flash */
-	sub	r3, r3, r1
-	add	r3, r3, r0
-	sub	r2, r2, r1
-	add	r2, r2, r0
-
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r7, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
 fixloop:
-	ldr	r4, [r2]
-	sub	r4, r4, r1
-	add	r4, r4, r0
-	str	r4, [r2]
-	add	r2, r2, #4
+	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r8, r1, #0xff
+	cmp	r8, #23		/* relative fixup? */
+	beq	fixrel
+	cmp	r8, #2		/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r9			/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 
 clear_bss:
-	ldr	r0, _bss_start
-	ldr	r1, _bss_end
+	ldr	r0, _bss_start_ofs
+	ldr	r1, _bss_end_ofs
 	ldr	r3, _TEXT_BASE		/* Text base */
 	mov	r4, r7			/* reloc addr */
-	sub	r0, r0, r3
 	add	r0, r0, r4
-	sub	r1, r1, r3
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
@@ -255,18 +272,26 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
  * initialization, now running from RAM.
  */
 jump_2_ram:
-	ldr	r0, _TEXT_BASE
-	ldr	r2, _board_init_r
-	sub	r2, r2, r0
-	add	r2, r2, r7	/* position from board_init_r in RAM */
+	ldr	r0, _board_init_r_ofs
+	adr	r1, _start
+	add	r0, r0, r1
+	add	lr, r0, r9
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r7		/* dest_addr */
 	/* jump to it ... */
-	mov	lr, r2
 	mov	pc, lr
 
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+	.word board_init_r - _start
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 /*
  * the actual reset code
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index d4fd3fc..88a0fec 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -53,6 +53,13 @@ SECTIONS
 	__datarelro_start = .;
 		*(.data.rel.ro)
 	}
+	. = ALIGN(4);
+	__rel_dyn_start = .;
+	.rel.dyn : { *(.rel.dyn) }
+	__rel_dyn_end = .;
+
+	__dynsym_start = .;
+	.dynsym : { *(.dynsym) }
 
 	__got_start = .;
 	. = ALIGN(4);
diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c
index 800d120..3ea3458 100644
--- a/arch/arm/cpu/pxa/cpu.c
+++ b/arch/arm/cpu/pxa/cpu.c
@@ -30,10 +30,11 @@
  * CPU specific code
  */
 
-#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
 #include <command.h>
+#include <common.h>
 #include <asm/arch/pxa-regs.h>
-#include <asm/system.h>
 
 static void cache_flush(void);
 
@@ -71,17 +72,249 @@ void set_GPIO_mode(int gpio_mode)
 {
 	int gpio = gpio_mode & GPIO_MD_MASK_NR;
 	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
-	int gafr;
+	int val;
+
+	/* This below changes direction setting of GPIO "gpio" */
+	val = readl(GPDR(gpio));
 
 	if (gpio_mode & GPIO_MD_MASK_DIR)
-	{
-		GPDR(gpio) |= GPIO_bit(gpio);
-	}
+		val |= GPIO_bit(gpio);
 	else
-	{
-		GPDR(gpio) &= ~GPIO_bit(gpio);
-	}
-	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
-	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
+		val &= ~GPIO_bit(gpio);
+
+	writel(val, GPDR(gpio));
+
+	/* This below updates only AF of GPIO "gpio" */
+	val = readl(GAFR(gpio));
+	val &= ~(0x3 << (((gpio) & 0xf) * 2));
+	val |= fn << (((gpio) & 0xf) * 2);
+	writel(val, GAFR(gpio));
 }
 #endif /* CONFIG_CPU_MONAHANS */
+
+void pxa_wait_ticks(int ticks)
+{
+	writel(0, OSCR);
+	while (readl(OSCR) < ticks)
+		asm volatile("":::"memory");
+}
+
+inline void writelrb(uint32_t val, uint32_t addr)
+{
+	writel(val, addr);
+	asm volatile("":::"memory");
+	readl(addr);
+	asm volatile("":::"memory");
+}
+
+void pxa_dram_init(void)
+{
+	uint32_t tmp;
+	int i;
+	/*
+	 * 1) Initialize Asynchronous static memory controller
+	 */
+
+	writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
+	writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
+	writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
+	/*
+	 * 2) Initialize Card Interface
+	 */
+
+	/* MECR: Memory Expansion Card Register */
+	writelrb(CONFIG_SYS_MECR_VAL, MECR);
+	/* MCMEM0: Card Interface slot 0 timing */
+	writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
+	/* MCMEM1: Card Interface slot 1 timing */
+	writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+	writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+	writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
+	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
+	writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
+	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
+	writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
+
+	/*
+	 * 3) Configure Fly-By DMA register
+	 */
+
+	writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
+
+	/*
+	 * 4) Initialize Timing for Sync Memory (SDCLK0)
+	 */
+
+	/*
+	 * Before accessing MDREFR we need a valid DRI field, so we set
+	 * this to power on defaults + DRI field.
+	 */
+
+	/* Read current MDREFR config and zero out DRI */
+	tmp = readl(MDREFR) & ~0xfff;
+	/* Add user-specified DRI */
+	tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
+	/* Configure important bits */
+	tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
+	tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
+
+	/* Write MDREFR back */
+	writelrb(tmp, MDREFR);
+
+	/*
+	 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+	 */
+
+	/* Initialize SXCNFG register. Assert the enable bits.
+	 *
+	 * Write SXMRS to cause an MRS command to all enabled banks of
+	 * synchronous static memory. Note that SXLCR need not be written
+	 * at this time.
+	 */
+	writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
+
+	/*
+	 * 6) Initialize SDRAM
+	 */
+
+	writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
+	writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
+
+	/*
+	 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+	 *    but not enable each SDRAM partition pair.
+	 */
+
+	writelrb(CONFIG_SYS_MDCNFG_VAL &
+		~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
+	/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+	pxa_wait_ticks(0x300);
+
+	/*
+	 * 8) Trigger a number (usually 8) refresh cycles by attempting
+	 *    non-burst read or write accesses to disabled SDRAM, as commonly
+	 *    specified in the power up sequence documented in SDRAM data
+	 *    sheets. The address(es) used for this purpose must not be
+	 *    cacheable.
+	 */
+	for (i = 9; i >= 0; i--) {
+		writel(i, 0xa0000000);
+		asm volatile("":::"memory");
+	}
+	/*
+	 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+	 */
+
+	tmp = CONFIG_SYS_MDCNFG_VAL &
+		(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
+	tmp |= readl(MDCNFG);
+	writelrb(tmp, MDCNFG);
+
+	/*
+	 * 10) Write MDMRS.
+	 */
+
+	writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
+
+	/*
+	 * 11) Enable APD
+	 */
+
+	if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
+		tmp = readl(MDREFR);
+		tmp |= MDREFR_APD;
+		writelrb(tmp, MDREFR);
+	}
+}
+
+void pxa_gpio_setup(void)
+{
+	writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
+	writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
+	writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
+#endif
+
+	writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
+	writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
+	writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
+#endif
+
+	writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
+	writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
+	writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
+#endif
+
+	writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
+	writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
+	writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
+	writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
+	writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
+	writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
+	writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
+#endif
+
+	writel(CONFIG_SYS_PSSR_VAL, PSSR);
+}
+
+void pxa_interrupt_setup(void)
+{
+	writel(0, ICLR);
+	writel(0, ICMR);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	writel(0, ICLR2);
+	writel(0, ICMR2);
+#endif
+}
+
+void pxa_clock_setup(void)
+{
+#ifndef CONFIG_CPU_MONAHANS
+	writel(CONFIG_SYS_CKEN, CKEN);
+	writel(CONFIG_SYS_CCCR, CCCR);
+	asm volatile("mcr	p14, 0, %0, c6, c0, 0"::"r"(2));
+#else
+/* Set CKENA/CKENB/ACCR for MH */
+#endif
+
+	/* enable the 32Khz oscillator for RTC and PowerManager */
+	writel(OSCC_OON, OSCC);
+	while(!(readl(OSCC) & OSCC_OOK))
+		asm volatile("":::"memory");
+}
+
+void pxa_wakeup(void)
+{
+	uint32_t rcsr;
+
+	rcsr = readl(RCSR);
+	writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
+
+	/* Wakeup */
+	if (rcsr & RCSR_SMR) {
+		writel(PSSR_PH, PSSR);
+		pxa_dram_init();
+		icache_disable();
+		dcache_disable();
+		asm volatile("mov	pc, %0"::"r"(readl(PSSR)));
+	}
+}
+
+int arch_cpu_init(void)
+{
+	pxa_gpio_setup();
+//	pxa_wait_ticks(0x8000);
+	pxa_wakeup();
+	pxa_interrupt_setup();
+	pxa_clock_setup();
+	return 0;
+}
diff --git a/arch/arm/cpu/pxa/i2c.c b/arch/arm/cpu/pxa/i2c.c
index 6b72ba1..7aa49ae 100644
--- a/arch/arm/cpu/pxa/i2c.c
+++ b/arch/arm/cpu/pxa/i2c.c
@@ -33,6 +33,7 @@
 /* FIXME: this file is PXA255 specific! What about other XScales? */
 
 #include <common.h>
+#include <asm/io.h>
 
 #ifdef CONFIG_HARD_I2C
 
@@ -93,19 +94,21 @@ struct i2c_msg {
 
 static void i2c_reset( void )
 {
-	ICR &= ~ICR_IUE;		/* disable unit */
-	ICR |= ICR_UR;			/* reset the unit */
+	writel(readl(ICR) & ~ICR_IUE, ICR);	/* disable unit */
+	writel(readl(ICR) | ICR_UR, ICR);	/* reset the unit */
 	udelay(100);
-	ICR &= ~ICR_IUE;		/* disable unit */
+	writel(readl(ICR) & ~ICR_IUE, ICR);	/* disable unit */
 #ifdef CONFIG_CPU_MONAHANS
-	CKENB |= (CKENB_4_I2C); /*  | CKENB_1_PWM1 | CKENB_0_PWM0); */
+	/* | CKENB_1_PWM1 | CKENB_0_PWM0); */
+	writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
 #else /* CONFIG_CPU_MONAHANS */
-	CKEN |= CKEN14_I2C;		/* set the global I2C clock on */
+	/* set the global I2C clock on */
+	writel(readl(CKEN) | CKEN14_I2C, CKEN);
 #endif
-	ISAR = I2C_PXA_SLAVE_ADDR;	/* set our slave address */
-	ICR = I2C_ICR_INIT;		/* set control register values */
-	ISR = I2C_ISR_INIT;		/* set clear interrupt bits */
-	ICR |= ICR_IUE;			/* enable unit */
+	writel(I2C_PXA_SLAVE_ADDR, ISAR);	/* set our slave address */
+	writel(I2C_ICR_INIT, ICR);		/* set control reg values */
+	writel(I2C_ISR_INIT, ISR);		/* set clear interrupt bits */
+	writel(readl(ICR) | ICR_IUE, ICR);	/* enable unit */
 	udelay(100);
 }
 
@@ -159,22 +162,26 @@ int i2c_transfer(struct i2c_msg *msg)
 			goto transfer_error_bus_busy;
 
 		/* start transmission */
-		ICR &= ~ICR_START;
-		ICR &= ~ICR_STOP;
-		IDBR = msg->data;
-		if (msg->condition == I2C_COND_START)     ICR |=  ICR_START;
-		if (msg->condition == I2C_COND_STOP)      ICR |=  ICR_STOP;
-		if (msg->acknack   == I2C_ACKNAK_SENDNAK) ICR |=  ICR_ACKNAK;
-		if (msg->acknack   == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
-		ICR &= ~ICR_ALDIE;
-		ICR |= ICR_TB;
+		writel(readl(ICR) & ~ICR_START, ICR);
+		writel(readl(ICR) & ~ICR_STOP, ICR);
+		writel(msg->data, IDBR);
+		if (msg->condition == I2C_COND_START)
+			writel(readl(ICR) | ICR_START, ICR);
+		if (msg->condition == I2C_COND_STOP)
+			writel(readl(ICR) | ICR_STOP, ICR);
+		if (msg->acknack == I2C_ACKNAK_SENDNAK)
+			writel(readl(ICR) | ICR_ACKNAK, ICR);
+		if (msg->acknack == I2C_ACKNAK_SENDACK)
+			writel(readl(ICR) & ~ICR_ACKNAK, ICR);
+		writel(readl(ICR) & ~ICR_ALDIE, ICR);
+		writel(readl(ICR) | ICR_TB, ICR);
 
 		/* transmit register empty? */
 		if (!i2c_isr_set_cleared(ISR_ITE,0))
 			goto transfer_error_transmit_timeout;
 
 		/* clear 'transmit empty' state */
-		ISR |= ISR_ITE;
+		writel(readl(ISR) | ISR_ITE, ISR);
 
 		/* wait for ACK from slave */
 		if (msg->acknack == I2C_ACKNAK_WAITACK)
@@ -189,23 +196,27 @@ int i2c_transfer(struct i2c_msg *msg)
 			goto transfer_error_bus_busy;
 
 		/* start receive */
-		ICR &= ~ICR_START;
-		ICR &= ~ICR_STOP;
-		if (msg->condition == I2C_COND_START)	  ICR |= ICR_START;
-		if (msg->condition == I2C_COND_STOP)	  ICR |= ICR_STOP;
-		if (msg->acknack   == I2C_ACKNAK_SENDNAK) ICR |=  ICR_ACKNAK;
-		if (msg->acknack   == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
-		ICR &= ~ICR_ALDIE;
-		ICR |= ICR_TB;
+		writel(readl(ICR) & ~ICR_START, ICR);
+		writel(readl(ICR) & ~ICR_STOP, ICR);
+		if (msg->condition == I2C_COND_START)
+			writel(readl(ICR) | ICR_START, ICR);
+		if (msg->condition == I2C_COND_STOP)
+			writel(readl(ICR) | ICR_STOP, ICR);
+		if (msg->acknack == I2C_ACKNAK_SENDNAK)
+			writel(readl(ICR) | ICR_ACKNAK, ICR);
+		if (msg->acknack == I2C_ACKNAK_SENDACK)
+			writel(readl(ICR) & ~ICR_ACKNAK, ICR);
+		writel(readl(ICR) & ~ICR_ALDIE, ICR);
+		writel(readl(ICR) | ICR_TB, ICR);
 
 		/* receive register full? */
 		if (!i2c_isr_set_cleared(ISR_IRF,0))
 			goto transfer_error_receive_timeout;
 
-		msg->data = IDBR;
+		msg->data = readl(IDBR);
 
 		/* clear 'receive empty' state */
-		ISR |= ISR_IRF;
+		writel(readl(ISR) | ISR_IRF, ISR);
 
 		break;
 
diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index 0ee6a75..987fa06 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -35,6 +35,7 @@
 #include <stdio_dev.h>
 #include <lcd.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 
 /* #define DEBUG */
 
@@ -56,26 +57,26 @@
 
 /* 640x480x16 @ 61 Hz */
 vidinfo_t panel_info = {
-	vl_col:		640,
-	vl_row:		480,
-	vl_width:	640,
-	vl_height:	480,
-	vl_clkp:	CONFIG_SYS_HIGH,
-	vl_oep:		CONFIG_SYS_HIGH,
-	vl_hsp:		CONFIG_SYS_HIGH,
-	vl_vsp:		CONFIG_SYS_HIGH,
-	vl_dp:		CONFIG_SYS_HIGH,
-	vl_bpix:	LCD_BPP,
-	vl_lbw:		0,
-	vl_splt:	0,
-	vl_clor:	0,
-	vl_tft:		1,
-	vl_hpw:		40,
-	vl_blw:		56,
-	vl_elw:		56,
-	vl_vpw:		20,
-	vl_bfw:		8,
-	vl_efw:		8,
+	.vl_col		= 640,
+	.vl_row		= 480,
+	.vl_width	= 640,
+	.vl_height	= 480,
+	.vl_clkp	= CONFIG_SYS_HIGH,
+	.vl_oep		= CONFIG_SYS_HIGH,
+	.vl_hsp		= CONFIG_SYS_HIGH,
+	.vl_vsp		= CONFIG_SYS_HIGH,
+	.vl_dp		= CONFIG_SYS_HIGH,
+	.vl_bpix	= LCD_BPP,
+	.vl_lbw		= 0,
+	.vl_splt	= 0,
+	.vl_clor	= 0,
+	.vl_tft		= 1,
+	.vl_hpw		= 40,
+	.vl_blw		= 56,
+	.vl_elw		= 56,
+	.vl_vpw		= 20,
+	.vl_bfw		= 8,
+	.vl_efw		= 8,
 };
 #endif /* CONFIG_PXA_VIDEO */
 
@@ -90,26 +91,26 @@ vidinfo_t panel_info = {
 # define REG_LCCR3	0x0340FF08
 
 vidinfo_t panel_info = {
-	vl_col:		640,
-	vl_row:		480,
-	vl_width:	157,
-	vl_height:	118,
-	vl_clkp:	CONFIG_SYS_HIGH,
-	vl_oep:		CONFIG_SYS_HIGH,
-	vl_hsp:		CONFIG_SYS_HIGH,
-	vl_vsp:		CONFIG_SYS_HIGH,
-	vl_dp:		CONFIG_SYS_HIGH,
-	vl_bpix:	LCD_BPP,
-	vl_lbw:		0,
-	vl_splt:	1,
-	vl_clor:	1,
-	vl_tft:		0,
-	vl_hpw:		1,
-	vl_blw:		3,
-	vl_elw:		3,
-	vl_vpw:		1,
-	vl_bfw:		0,
-	vl_efw:		0,
+	.vl_col		= 640,
+	.vl_row		= 480,
+	.vl_width	= 157,
+	.vl_height	= 118,
+	.vl_clkp	= CONFIG_SYS_HIGH,
+	.vl_oep		= CONFIG_SYS_HIGH,
+	.vl_hsp		= CONFIG_SYS_HIGH,
+	.vl_vsp		= CONFIG_SYS_HIGH,
+	.vl_dp		= CONFIG_SYS_HIGH,
+	.vl_bpix	= LCD_BPP,
+	.vl_lbw		= 0,
+	.vl_splt	= 1,
+	.vl_clor	= 1,
+	.vl_tft		= 0,
+	.vl_hpw		= 1,
+	.vl_blw		= 3,
+	.vl_elw		= 3,
+	.vl_vpw		= 1,
+	.vl_bfw		= 0,
+	.vl_efw		= 0,
 };
 #endif /* CONFIG_SHARP_LM8V31 */
 /*----------------------------------------------------------------------*/
@@ -123,26 +124,26 @@ vidinfo_t panel_info = {
 # define REG_LCCR3	0x0340FF08
 
 vidinfo_t panel_info = {
-	vl_col:		640,
-	vl_row:		480,
-	vl_width:	157,
-	vl_height:	118,
-	vl_clkp:	CONFIG_SYS_HIGH,
-	vl_oep:		CONFIG_SYS_HIGH,
-	vl_hsp:		CONFIG_SYS_HIGH,
-	vl_vsp:		CONFIG_SYS_HIGH,
-	vl_dp:		CONFIG_SYS_HIGH,
-	vl_bpix:	LCD_BPP,
-	vl_lbw:		0,
-	vl_splt:	1,
-	vl_clor:	1,
-	vl_tft:		1,
-	vl_hpw:		32,
-	vl_blw:		144,
-	vl_elw:		32,
-	vl_vpw:		2,
-	vl_bfw:		13,
-	vl_efw:		30,
+	.vl_col		= 640,
+	.vl_row		= 480,
+	.vl_width	= 157,
+	.vl_height	= 118,
+	.vl_clkp	= CONFIG_SYS_HIGH,
+	.vl_oep		= CONFIG_SYS_HIGH,
+	.vl_hsp		= CONFIG_SYS_HIGH,
+	.vl_vsp		= CONFIG_SYS_HIGH,
+	.vl_dp		= CONFIG_SYS_HIGH,
+	.vl_bpix	= LCD_BPP,
+	.vl_lbw		= 0,
+	.vl_splt	= 1,
+	.vl_clor	= 1,
+	.vl_tft		= 1,
+	.vl_hpw		= 32,
+	.vl_blw		= 144,
+	.vl_elw		= 32,
+	.vl_vpw		= 2,
+	.vl_bfw		= 13,
+	.vl_efw		= 30,
 };
 #endif /* CONFIG_VOIPAC_LCD */
 
@@ -156,26 +157,26 @@ vidinfo_t panel_info = {
 #define REG_LCCR3	0x0340FF20
 
 vidinfo_t panel_info = {
-	vl_col:		320,
-	vl_row:		240,
-	vl_width:	167,
-	vl_height:	109,
-	vl_clkp:	CONFIG_SYS_HIGH,
-	vl_oep:		CONFIG_SYS_HIGH,
-	vl_hsp:		CONFIG_SYS_HIGH,
-	vl_vsp:		CONFIG_SYS_HIGH,
-	vl_dp:		CONFIG_SYS_HIGH,
-	vl_bpix:	LCD_BPP,
-	vl_lbw:		1,
-	vl_splt:	0,
-	vl_clor:	1,
-	vl_tft:		0,
-	vl_hpw:		1,
-	vl_blw:		1,
-	vl_elw:		1,
-	vl_vpw:		7,
-	vl_bfw:		0,
-	vl_efw:		0,
+	.vl_col		= 320,
+	.vl_row		= 240,
+	.vl_width	= 167,
+	.vl_height	= 109,
+	.vl_clkp	= CONFIG_SYS_HIGH,
+	.vl_oep		= CONFIG_SYS_HIGH,
+	.vl_hsp		= CONFIG_SYS_HIGH,
+	.vl_vsp		= CONFIG_SYS_HIGH,
+	.vl_dp		= CONFIG_SYS_HIGH,
+	.vl_bpix	= LCD_BPP,
+	.vl_lbw		= 1,
+	.vl_splt	= 0,
+	.vl_clor	= 1,
+	.vl_tft		= 0,
+	.vl_hpw		= 1,
+	.vl_blw		= 1,
+	.vl_elw		= 1,
+	.vl_vpw		= 7,
+	.vl_bfw		= 0,
+	.vl_efw		= 0,
 };
 #endif /* CONFIG_HITACHI_SX14 */
 
@@ -190,31 +191,132 @@ vidinfo_t panel_info = {
 # define REG_LCCR3	0x03b00009
 
 vidinfo_t panel_info = {
-	vl_col:		240,
-	vl_row:		320,
-	vl_width:	240,
-	vl_height:	320,
-	vl_clkp:	CONFIG_SYS_HIGH,
-	vl_oep:		CONFIG_SYS_LOW,
-	vl_hsp:		CONFIG_SYS_LOW,
-	vl_vsp:		CONFIG_SYS_LOW,
-	vl_dp:		CONFIG_SYS_HIGH,
-	vl_bpix:	LCD_BPP,
-	vl_lbw:		0,
-	vl_splt:	1,
-	vl_clor:	1,
-	vl_tft:		1,
-	vl_hpw:		4,
-	vl_blw:		4,
-	vl_elw:		8,
-	vl_vpw:		4,
-	vl_bfw:		4,
-	vl_efw:		8,
+	.vl_col		= 240,
+	.vl_row		= 320,
+	.vl_width	= 240,
+	.vl_height	= 320,
+	.vl_clkp	= CONFIG_SYS_HIGH,
+	.vl_oep		= CONFIG_SYS_LOW,
+	.vl_hsp		= CONFIG_SYS_LOW,
+	.vl_vsp		= CONFIG_SYS_LOW,
+	.vl_dp		= CONFIG_SYS_HIGH,
+	.vl_bpix	= LCD_BPP,
+	.vl_lbw		= 0,
+	.vl_splt	= 1,
+	.vl_clor	= 1,
+	.vl_tft		= 1,
+	.vl_hpw		= 4,
+	.vl_blw		= 4,
+	.vl_elw		= 8,
+	.vl_vpw		= 4,
+	.vl_bfw		= 4,
+	.vl_efw		= 8,
 };
 #endif /* CONFIG_LMS283GF05 */
 
 /*----------------------------------------------------------------------*/
 
+#ifdef CONFIG_ACX517AKN
+
+# define LCD_BPP	LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0	0x003008f9
+# define REG_LCCR3	0x03700006
+
+vidinfo_t panel_info = {
+	.vl_col		= 320,
+	.vl_row		= 320,
+	.vl_width	= 320,
+	.vl_height	= 320,
+	.vl_clkp	= CONFIG_SYS_HIGH,
+	.vl_oep		= CONFIG_SYS_LOW,
+	.vl_hsp		= CONFIG_SYS_LOW,
+	.vl_vsp		= CONFIG_SYS_LOW,
+	.vl_dp		= CONFIG_SYS_HIGH,
+	.vl_bpix	= LCD_BPP,
+	.vl_lbw		= 0,
+	.vl_splt	= 1,
+	.vl_clor	= 1,
+	.vl_tft		= 1,
+	.vl_hpw		= 0x04,
+	.vl_blw		= 0x1c,
+	.vl_elw		= 0x08,
+	.vl_vpw		= 0x01,
+	.vl_bfw		= 0x07,
+	.vl_efw		= 0x08,
+};
+#endif /* CONFIG_ACX517AKN */
+
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_LQ038J7DH53
+
+# define LCD_BPP	LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0	0x003008f9
+# define REG_LCCR3	0x03700004
+
+vidinfo_t panel_info = {
+	.vl_col		= 320,
+	.vl_row		= 480,
+	.vl_width	= 320,
+	.vl_height	= 480,
+	.vl_clkp	= CONFIG_SYS_HIGH,
+	.vl_oep		= CONFIG_SYS_LOW,
+	.vl_hsp		= CONFIG_SYS_LOW,
+	.vl_vsp		= CONFIG_SYS_LOW,
+	.vl_dp		= CONFIG_SYS_HIGH,
+	.vl_bpix	= LCD_BPP,
+	.vl_lbw		= 0,
+	.vl_splt	= 1,
+	.vl_clor	= 1,
+	.vl_tft		= 1,
+	.vl_hpw		= 0x04,
+	.vl_blw		= 0x20,
+	.vl_elw		= 0x01,
+	.vl_vpw		= 0x01,
+	.vl_bfw		= 0x04,
+	.vl_efw		= 0x01,
+};
+#endif /* CONFIG_ACX517AKN */
+
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_LITTLETON_LCD
+# define LCD_BPP	LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0	0x003008f8
+# define REG_LCCR3	0x0300FF04
+
+vidinfo_t panel_info = {
+	.vl_col		= 480,
+	.vl_row		= 640,
+	.vl_width	= 480,
+	.vl_height	= 640,
+	.vl_clkp	= CONFIG_SYS_HIGH,
+	.vl_oep		= CONFIG_SYS_HIGH,
+	.vl_hsp		= CONFIG_SYS_HIGH,
+	.vl_vsp		= CONFIG_SYS_HIGH,
+	.vl_dp		= CONFIG_SYS_HIGH,
+	.vl_bpix	= LCD_BPP,
+	.vl_lbw		= 0,
+	.vl_splt	= 0,
+	.vl_clor	= 0,
+	.vl_tft		= 1,
+	.vl_hpw		= 9,
+	.vl_blw		= 8,
+	.vl_elw		= 24,
+	.vl_vpw		= 2,
+	.vl_bfw		= 2,
+	.vl_efw		= 4,
+};
+#endif /* CONFIG_LITTLETON_LCD */
+
+/*----------------------------------------------------------------------*/
+
 #if LCD_BPP == LCD_COLOR8
 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
 #endif
@@ -377,12 +479,14 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
 	{
 		debug("Setting GPIO for 4 bit data\n");
 		/* bits 58-61 */
-		GPDR1 |= (0xf << 26);
-		GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
+		writel(readl(GPDR1) | (0xf << 26), GPDR1);
+		writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
+			GAFR1_U);
 
 		/* bits 74-77 */
-		GPDR2 |= (0xf << 10);
-		GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
+		writel(readl(GPDR2) | (0xf << 10), GPDR2);
+		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
+			GAFR2_L);
 	}
 
 	/* 8 bit interface */
@@ -391,15 +495,17 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
 	{
 		debug("Setting GPIO for 8 bit data\n");
 		/* bits 58-65 */
-		GPDR1 |= (0x3f << 26);
-		GPDR2 |= (0x3);
+		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
+		writel(readl(GPDR2) | (0x3), GPDR2);
 
-		GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
-		GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
+		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
+			GAFR1_U);
+		writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
 
 		/* bits 74-77 */
-		GPDR2 |= (0xf << 10);
-		GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
+		writel(readl(GPDR2) | (0xf << 10), GPDR2);
+		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
+			GAFR2_L);
 	}
 
 	/* 16 bit interface */
@@ -407,11 +513,12 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
 	{
 		debug("Setting GPIO for 16 bit data\n");
 		/* bits 58-77 */
-		GPDR1 |= (0x3f << 26);
-		GPDR2 |= 0x00003fff;
+		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
+		writel(readl(GPDR2) | 0x00003fff, GPDR2);
 
-		GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
-		GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
+		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
+			GAFR1_U);
+		writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
 	}
 	else
 	{
@@ -425,26 +532,26 @@ static void pxafb_enable_controller (vidinfo_t *vid)
 	debug("Enabling LCD controller\n");
 
 	/* Sequence from 11.7.10 */
-	LCCR3  = vid->pxa.reg_lccr3;
-	LCCR2  = vid->pxa.reg_lccr2;
-	LCCR1  = vid->pxa.reg_lccr1;
-	LCCR0  = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
-	FDADR0 = vid->pxa.fdadr0;
-	FDADR1 = vid->pxa.fdadr1;
-	LCCR0 |= LCCR0_ENB;
+	writel(vid->pxa.reg_lccr3, LCCR3);
+	writel(vid->pxa.reg_lccr2, LCCR2);
+	writel(vid->pxa.reg_lccr1, LCCR1);
+	writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
+	writel(vid->pxa.fdadr0, FDADR0);
+	writel(vid->pxa.fdadr1, FDADR1);
+	writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
 
 #ifdef	CONFIG_CPU_MONAHANS
-	CKENA |= CKENA_1_LCD;
+	writel(readl(CKENA) | CKENA_1_LCD, CKENA);
 #else
-	CKEN |= CKEN16_LCD;
+	writel(readl(CKEN) | CKEN16_LCD, CKEN);
 #endif
 
-	debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
-	debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
-	debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
-	debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
-	debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
-	debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
+	debug("FDADR0 = 0x%08x\n", readl(FDADR0));
+	debug("FDADR1 = 0x%08x\n", readl(FDADR1));
+	debug("LCCR0 = 0x%08x\n", readl(LCCR0));
+	debug("LCCR1 = 0x%08x\n", readl(LCCR1));
+	debug("LCCR2 = 0x%08x\n", readl(LCCR2));
+	debug("LCCR3 = 0x%08x\n", readl(LCCR3));
 }
 
 static int pxafb_init (vidinfo_t *vid)
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 9c5023b..684e44e 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -31,6 +31,14 @@
 #include <config.h>
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
+
+/* takes care the CP15 update has taken place */
+.macro CPWAIT reg
+mrc  p15,0,\reg,c2,c0,0
+mov  \reg,\reg
+sub  pc,pc,#4
+.endm
 
 .globl _start
 _start: b	reset
@@ -86,11 +94,9 @@ _fiq:			.word fiq
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 .globl _armboot_start
 _armboot_start:
 	.word _start
-#endif
 
 /*
  * These are defined in the board-specific linker script.
@@ -115,7 +121,7 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif /* CONFIG_USE_IRQ */
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
+#ifndef CONFIG_PRELOADER
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -159,12 +165,84 @@ reset:
 	msr	cpsr,r0
 
 	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
+	 * Enable MMU to use DCache as DRAM
 	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
+	/* Domain access -- enable for all CPs */
+	ldr	r0, =0x0000ffff
+	mcr	p15, 0, r0, c3, c0, 0
+
+	/* Point TTBR to MMU table */
+	ldr	r0, =mmu_table
+	adr	r2, _start
+	orr	r0, r2
+	mcr	p15, 0, r0, c2, c0, 0
+
+/* !!! Hereby, check if the code is running from SRAM !!! */
+/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
+ * is linked to 0x0 too, so this makes things easier. */
+	cmp	r2, #0x5c000000
+
+	ldreq	r1, [r0]
+	orreq	r1, r2
+	streq	r1, [r0]
+
+	/* Kick in MMU, ICache, DCache, BTB */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, #0x1b00
+	bic	r0, #0x0087
+	orr	r0, #0x1800
+	orr	r0, #0x0005
+	mcr	p15, 0, r0, c1, c0, 0
+	CPWAIT	r0
+
+	/* Unlock Icache, Dcache */
+	mcr	p15, 0, r0, c9, c1, 1
+	mcr	p15, 0, r0, c9, c2, 1
+
+	/* Flush Icache, Dcache, BTB */
+	mcr	p15, 0, r0, c7, c7, 0
+
+	/* Unlock I-TLB, D-TLB */
+	mcr	p15, 0, r0, c10, c4, 1
+	mcr	p15, 0, r0, c10, c8, 1
+
+	/* Flush TLB */
+	mcr	p15, 0, r0, c8, c7, 0
+	/* Allocate 4096 bytes of Dcache as RAM */
+
+	/* Drain pending loads and stores */
+	mcr	p15, 0, r0, c7, c10, 4
+
+	mov	r4, #0x00
+	mov	r5, #0x00
+	mov	r2, #0x01
+	mcr	p15, 0, r0, c9, c2, 0
+	CPWAIT	r0
+
+	/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
+	mov	r0, #128
+	mov	r1, #0xa0000000
+alloc:
+	mcr	p15, 0, r1, c7, c2, 5
+	/* Drain pending loads and stores */
+	mcr	p15, 0, r0, c7, c10, 4
+	strd	r4, [r1], #8
+	strd	r4, [r1], #8
+	strd	r4, [r1], #8
+	strd	r4, [r1], #8
+	subs	r0, #0x01
+	bne	alloc
+	/* Drain pending loads and stores */
+	mcr	p15, 0, r0, c7, c10, 4
+	mov	r2, #0x00
+	mcr	p15, 0, r2, c9, c2, 0
+	CPWAIT	r0
+
+	/* Jump to 0x0 ( + offset) if running from SRAM */
+	adr	r0, zerojmp
+	bic	r0, #0x5c000000
+	mov	pc, r0
+zerojmp:
 
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
@@ -201,11 +279,13 @@ stack_setup:
 	beq	clear_bss
 
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
+	stmfd sp!, {r0-r12}
 copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
+	ldmia	r0!, {r3-r5, r7-r11}	/* copy from source address [r0]    */
+	stmia	r6!, {r3-r5, r7-r11}	/* copy to   target address [r1]    */
 	cmp	r0, r2			/* until source end address [r2]    */
 	blo	copy_loop
+	ldmfd sp!, {r0-r12}
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -274,218 +354,28 @@ _board_init_r: .word board_init_r
 
 /****************************************************************************/
 /*									    */
-/* the actual reset code						    */
+/* the actual reset code for OneNAND IPL				    */
 /*									    */
 /****************************************************************************/
 
+#ifndef	CONFIG_PXA27X
+#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
+#endif
+
 reset:
-	mrs	r0,cpsr			/* set the CPU to SVC32 mode	    */
-	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)	    */
+	/* Set CPU to SVC32 mode */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
 	orr	r0,r0,#0x13
 	msr	cpsr,r0
 
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from RAM!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit		/* we do sys-critical inits	    */
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-#ifndef	CONFIG_PRELOADER
-	cmp	r0, r1			/* don't reloc during debug	    */
-	beq	stack_setup
-#endif
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot	    */
-	add	r2, r0, r2		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
+	/* Point stack at the end of SRAM and leave 32 words for abort-stack */
+	ldr	sp, =0x5c03ff80
 
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-#ifdef CONFIG_PRELOADER
-	sub	sp, r0, #128		/* leave 32 words for abort-stack   */
-#else
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area		    */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo		    */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif /* CONFIG_USE_IRQ */
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-#endif
+	/* Start OneNAND IPL */
+	ldr	pc, =start_oneboot
 
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment	    */
-	ldr	r1, _bss_end		/* stop here			    */
-	mov	r2, #0x00000000		/* clear			    */
-
-#ifndef CONFIG_PRELOADER
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-#endif
-
-	ldr	pc, _start_armboot
-
-#ifdef CONFIG_ONENAND_IPL
-_start_armboot: .word start_oneboot
-#else
-_start_armboot: .word start_armboot
-#endif
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/****************************************************************************/
-/*									    */
-/* CPU_init_critical registers						    */
-/*									    */
-/* - setup important registers						    */
-/* - setup memory timing						    */
-/*									    */
-/****************************************************************************/
-/* mk@tbd: Fix this! */
-#undef RCSR
-#undef ICMR
-#undef OSMR3
-#undef OSCR
-#undef OWER
-#undef OIER
-#undef CCCR
-
-/* Interrupt-Controller base address					    */
-IC_BASE:	   .word	   0x40d00000
-#define ICMR	0x04
-
-/* Reset-Controller */
-RST_BASE:	.word	0x40f00030
-#define RCSR	0x00
-
-/* Operating System Timer */
-OSTIMER_BASE:	.word	0x40a00000
-#define OSMR3	0x0C
-#define OSCR	0x10
-#define OWER	0x18
-#define OIER	0x1C
-
-/* Clock Manager Registers						    */
-#ifdef CONFIG_CPU_MONAHANS
-# ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
-#  error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!"
-# endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */
-# ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
-#  define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
-# endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */
-#else /* !CONFIG_CPU_MONAHANS */
-#ifdef CONFIG_SYS_CPUSPEED
-CC_BASE:	.word	0x41300000
-#define CCCR	0x00
-cpuspeed:	.word	CONFIG_SYS_CPUSPEED
-#else /* !CONFIG_SYS_CPUSPEED */
-#error "You have to define CONFIG_SYS_CPUSPEED!!"
-#endif /* CONFIG_SYS_CPUSPEED */
-#endif /* CONFIG_CPU_MONAHANS */
-
-	/* takes care the CP15 update has taken place */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-cpu_init_crit:
-
-	/* mask all IRQs						    */
-#ifndef CONFIG_CPU_MONAHANS
-	ldr	r0, IC_BASE
-	mov	r1, #0x00
-	str	r1, [r0, #ICMR]
-#else /* CONFIG_CPU_MONAHANS */
-	/* Step 1 - Enable CP6 permission */
-	mrc	p15, 0, r1, c15, c1, 0	@ read CPAR
-	orr	r1, r1, #0x40
-		mcr	p15, 0, r1, c15, c1, 0
-	CPWAIT	r1
-
-	/* Step 2 - Mask ICMR & ICMR2 */
-	mov	r1, #0
-	mcr	p6, 0, r1, c1, c0, 0	@ ICMR
-	mcr	p6, 0, r1, c7, c0, 0	@ ICMR2
-
-	/* turn off all clocks but the ones we will definitly require */
-	ldr	r1, =CKENA
-	ldr	r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
-	str	r2, [r1]
-	ldr	r1, =CKENB
-	ldr	r2, =(CKENB_6_IRQ)
-	str	r2, [r1]
-#endif /* !CONFIG_CPU_MONAHANS */
-
-	/* set clock speed */
-#ifdef CONFIG_CPU_MONAHANS
-	ldr	r0, =ACCR
-	ldr	r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
-	str	r1, [r0]
-#else /* !CONFIG_CPU_MONAHANS */
-#ifdef CONFIG_SYS_CPUSPEED
-	ldr	r0, CC_BASE
-	ldr	r1, cpuspeed
-	str	r1, [r0, #CCCR]
-	mov	r0, #2
-	mcr	p14, 0, r0, c6, c0, 0
-
-setspeed_done:
-
-#endif /* CONFIG_SYS_CPUSPEED */
-#endif /* CONFIG_CPU_MONAHANS */
-
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	mov	ip,	lr
-	bl	lowlevel_init
-	mov	lr,	ip
-
-	/* Memory interfaces are working. Disable MMU and enable I-cache.   */
-	/* mk: hmm, this is not in the monahans docs, leave it now but
-	 *     check here if it doesn't work :-) */
-
-	ldr	r0, =0x2001		/* enable access to all coproc.	    */
-	mcr	p15, 0, r0, c15, c1, 0
-	CPWAIT r0
-
-	mcr	p15, 0, r0, c7, c10, 4	/* drain the write & fill buffers   */
-	CPWAIT r0
-
-	mcr	p15, 0, r0, c7, c7, 0	/* flush Icache, Dcache and BTB	    */
-	CPWAIT r0
-
-	mcr	p15, 0, r0, c8, c7, 0	/* flush instuction and data TLBs   */
-	CPWAIT r0
-
-	/* Enable the Icache						    */
-/*
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #0x1800
-	mcr	p15, 0, r0, c1, c0, 0
-	CPWAIT
-*/
-	mov	pc, lr
+#endif /* #if !defined(CONFIG_ONENAND_IPL) */
 
 #ifndef CONFIG_PRELOADER
 /****************************************************************************/
@@ -676,6 +566,12 @@ fiq:
 /* perform a watchdog timeout for a soft reset.				    */
 /*									    */
 /****************************************************************************/
+/* Operating System Timer */
+OSTIMER_BASE:	.word	0x40a00000
+#define OSMR3	0x0C
+#define OSCR	0x10
+#define OWER	0x18
+#define OIER	0x1C
 
 	.align	5
 .globl reset_cpu
@@ -703,3 +599,25 @@ reset_cpu:
 reset_endless:
 
 	b	reset_endless
+
+#ifndef CONFIG_PRELOADER
+.section .mmudata, "a"
+	.align	14
+	.globl	mmu_table
+mmu_table:
+	/* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
+	.set	__base, 0
+	.rept	0xa00
+	.word	(__base << 20) | 0xc12
+	.set	__base, __base + 1
+	.endr
+
+	/* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
+	.word	(0xa00 << 20) | 0x1c1e
+
+	.set	__base, 0xa01
+	.rept	0x1000 - 0xa01
+	.word	(__base << 20) | 0xc12
+	.set	__base, __base + 1
+	.endr
+#endif
diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c
index 8d0f826..ec950c7 100644
--- a/arch/arm/cpu/pxa/timer.c
+++ b/arch/arm/cpu/pxa/timer.c
@@ -26,8 +26,9 @@
  * MA 02111-1307 USA
  */
 
-#include <common.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+#include <common.h>
 #include <div64.h>
 
 #ifdef CONFIG_USE_IRQ
@@ -86,7 +87,7 @@ void __udelay (unsigned long usec)
 
 void reset_timer_masked (void)
 {
-	OSCR = 0;
+	writel(0, OSCR);
 }
 
 ulong get_timer_masked (void)
@@ -113,7 +114,7 @@ void udelay_masked (unsigned long usec)
  */
 unsigned long long get_ticks(void)
 {
-	return OSCR;
+	return readl(OSCR);
 }
 
 /*
diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c
index bd718a6..0311d5e 100644
--- a/arch/arm/cpu/pxa/usb.c
+++ b/arch/arm/cpu/pxa/usb.c
@@ -27,86 +27,79 @@
 # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 #include <usb.h>
 
 int usb_cpu_init(void)
 {
 #if defined(CONFIG_CPU_MONAHANS)
 	/* Enable USB host clock. */
-	CKENA |= (CKENA_2_USBHOST |  CKENA_20_UDC);
+	writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
 	udelay(100);
 #endif
 #if defined(CONFIG_PXA27X)
 	/* Enable USB host clock. */
-	CKEN |= CKEN10_USBHOST;
+	writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
 #endif
 
 #if defined(CONFIG_CPU_MONAHANS)
 	/* Configure Port 2 for Host (USB Client Registers) */
-	UP2OCR = 0x3000c;
+	writel(0x3000c, UP2OCR);
 #endif
 
-	UHCHR |= UHCHR_FHR;
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 	wait_ms(11);
-	UHCHR &= ~UHCHR_FHR;
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
-	UHCHR |= UHCHR_FSBIR;
-	while (UHCHR & UHCHR_FSBIR)
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+	while (readl(UHCHR) & UHCHR_FSBIR)
 		udelay(1);
 
 #if defined(CONFIG_CPU_MONAHANS)
-	UHCHR &= ~UHCHR_SSEP0;
+	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
 #endif
 #if defined(CONFIG_PXA27X)
-	UHCHR &= ~UHCHR_SSEP2;
+	writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
 #endif
-	UHCHR &= ~UHCHR_SSEP1;
-	UHCHR &= ~UHCHR_SSE;
+	writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
 
 	return 0;
 }
 
 int usb_cpu_stop(void)
 {
-	UHCHR |= UHCHR_FHR;
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 	udelay(11);
-	UHCHR &= ~UHCHR_FHR;
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
-	UHCCOMS |= 1;
+	writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS);
 	udelay(10);
 
 #if defined(CONFIG_CPU_MONAHANS)
-	UHCHR |= UHCHR_SSEP0;
+	writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
 #endif
 #if defined(CONFIG_PXA27X)
-	UHCHR |= UHCHR_SSEP2;
+	writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
 #endif
-	UHCHR |= UHCHR_SSEP1;
-	UHCHR |= UHCHR_SSE;
-
-	return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-	UHCHR |= UHCHR_FHR;
-	udelay(11);
-	UHCHR &= ~UHCHR_FHR;
-
-	UHCCOMS |= 1;
-	udelay(10);
+	writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
 
 #if defined(CONFIG_CPU_MONAHANS)
-	UHCHR |= UHCHR_SSEP0;
+	/* Disable USB host clock. */
+	writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
+	udelay(100);
 #endif
 #if defined(CONFIG_PXA27X)
-	UHCHR |= UHCHR_SSEP2;
+	/* Disable USB host clock. */
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 #endif
-	UHCHR |= UHCHR_SSEP1;
-	UHCHR |= UHCHR_SSE;
 
 	return 0;
 }
 
+int usb_cpu_init_fail(void)
+{
+	return usb_cpu_stop();
+}
+
 # endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h
index 9f732a7..f5f80e0 100644
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ b/arch/arm/include/asm/arch-at91/hardware.h
@@ -18,6 +18,7 @@
 
 #if defined(CONFIG_AT91RM9200)
 #include <asm/arch-at91/at91rm9200.h>
+#define AT91_PMC_UHP	AT91RM9200_PMC_UHP
 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
 #include <asm/arch/at91sam9260.h>
 #define AT91_BASE_MCI	AT91SAM9260_BASE_MCI
diff --git a/arch/arm/include/asm/arch-mx51/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h
index afd2728..afd2728 100644
--- a/arch/arm/include/asm/arch-mx51/asm-offsets.h
+++ b/arch/arm/include/asm/arch-mx5/asm-offsets.h
diff --git a/arch/arm/include/asm/arch-mx51/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 1f8a537..1f8a537 100644
--- a/arch/arm/include/asm/arch-mx51/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
diff --git a/arch/arm/include/asm/arch-mx51/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 14aa231..14aa231 100644
--- a/arch/arm/include/asm/arch-mx51/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 3ddda40..3ddda40 100644
--- a/arch/arm/include/asm/arch-mx51/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
diff --git a/arch/arm/include/asm/arch-mx51/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h
index a41c387..0d91a24 100644
--- a/arch/arm/include/asm/arch-mx51/iomux.h
+++ b/arch/arm/include/asm/arch-mx5/iomux.h
@@ -20,13 +20,13 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __MACH_MX51_IOMUX_H__
-#define __MACH_MX51_IOMUX_H__
+#ifndef __MACH_MX5_IOMUX_H__
+#define __MACH_MX5_IOMUX_H__
 
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
 
 typedef unsigned int iomux_pin_name_t;
 
@@ -190,4 +190,4 @@ void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
 unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
 void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
 
-#endif				/*  __MACH_MX51_IOMUX_H__ */
+#endif				/*  __MACH_MX5_IOMUX_H__ */
diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
index b44ff25..a564fce 100644
--- a/arch/arm/include/asm/arch-mx51/mx51_pins.h
+++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
@@ -20,8 +20,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
-#define __ASM_ARCH_MXC_MX51_PINS_H__
+#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
+#define __ASM_ARCH_MX5_MX5X_PINS_H__
 
 #ifndef __ASSEMBLY__
 
@@ -415,4 +415,4 @@ enum iomux_pins {
 };
 
 #endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_ARCH_MXC_MX51_PINS_H__ */
+#endif				/* __ASM_ARCH_MX5_MX5X_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index f687503..f687503 100644
--- a/arch/arm/include/asm/arch-mx51/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h
index c8c479a..44b800f 100644
--- a/arch/arm/include/asm/arch-pxa/hardware.h
+++ b/arch/arm/include/asm/arch-pxa/hardware.h
@@ -21,6 +21,19 @@
 #include <linux/config.h>
 #include <asm/mach-types.h>
 
+/*
+ * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
+ * PXA300/310/320 all have distinct register mappings in some cases, that's why
+ * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
+ * drivers and compatibility glue with old source then.
+ */
+#ifndef	CONFIG_CPU_MONAHANS
+#if	defined(CONFIG_CPU_PXA300) || \
+	defined(CONFIG_CPU_PXA310) || \
+	defined(CONFIG_CPU_PXA320)
+#define	CONFIG_CPU_MONAHANS
+#endif
+#endif
 
 /*
  * These are statically mapped PCMCIA IO space for designs using it as a
@@ -51,54 +64,6 @@
  * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
  */
 
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-
-#ifndef UBOOT_REG_FIX
-#ifndef __ASSEMBLY__
-
-#define io_p2v(x)	( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
-#define io_v2p( x )	( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
-
-/*
- * This __REG() version gives the same results as the one above,  except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers.  It's a shame that gcc
- * doesn't guess this by itself.
- */
-#include <asm/types.h>
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x)	((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x)	__REGP(io_p2v(x))
-#endif
-
-/* Let's kick gcc's ass again... */
-# define __REG2(x,y)	\
-	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
-				  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
-
-# define __PREG(x)	(io_v2p((u32)&(x)))
-
-#else
-
-# define __REG(x)	io_p2v(x)
-# define __PREG(x)	io_v2p(x)
-
-# undef io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-#  define io_p2v(PhAdd)	   (PhAdd)
-#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
-#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-#  define __REG(x) (x)
-#  ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */
-#   define __REG_2(x) (x)
-#   define __REG_3(x) (x)
-#  endif
-# endif
-#endif /* UBOOT_REG_FIX */
-
 #include "pxa-regs.h"
 
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h
index 035a57e..85958dd 100644
--- a/arch/arm/include/asm/arch-pxa/macro.h
+++ b/arch/arm/include/asm/arch-pxa/macro.h
@@ -102,7 +102,11 @@
 /*
  * This macro sets up the Memory controller of the PXA2xx CPU
  *
- * Clobbered regs: r3, r4, r5
+ * WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
+ *          and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
+ *          use this regs for other purpose inside this macro.
+ *
+ * Clobbered regs: r3, r4, r5, r6, r7
  */
 .macro	pxa_mem_setup
 	/* This comes handy when setting MDREFR */
@@ -157,7 +161,7 @@
 	bic	r5, r5, #0xf00	/* MDREFR user config with zeroed DRI */
 
 	ldr	r4, =CONFIG_SYS_MDREFR_VAL
-	mov	r6, r4
+	mov	r7, r4
 	lsl	r4, #20
 	lsr	r4, #20		/* Get a valid DRI field */
 
@@ -187,12 +191,12 @@
 	 * 6) Initialize SDRAM
 	 */
 
-	bic	r6, #MDREFR_SLFRSH
-	str	r6, [r3, #MDREFR_OFFSET]
+	bic	r7, #MDREFR_SLFRSH
+	str	r7, [r3, #MDREFR_OFFSET]
 	ldr	r4, [r3, #MDREFR_OFFSET]
 
-	orr	r6, #MDREFR_E1PIN
-	str	r6, [r3, #MDREFR_OFFSET]
+	orr	r7, #MDREFR_E1PIN
+	str	r7, [r3, #MDREFR_OFFSET]
 	ldr	r4, [r3, #MDREFR_OFFSET]
 
 	/*
@@ -250,8 +254,8 @@
 	 */
 
 	ldr	r4, [r3, #MDREFR_OFFSET]
-	and	r6, r6, #MDREFR_APD
-	orr	r4, r4, r6
+	and	r7, r7, #MDREFR_APD
+	orr	r4, r4, r7
 	str	r4, [r3, #MDREFR_OFFSET]
 	ldr	r4, [r3, #MDREFR_OFFSET]
 .endm
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index d442fb0..65a387f 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -93,42 +93,42 @@ typedef void		(*ExcpHndlr) (void) ;
 /*
  * DMA Controller
  */
-#define DCSR0		__REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
-#define DCSR1		__REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
-#define DCSR2		__REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
-#define DCSR3		__REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
-#define DCSR4		__REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */
-#define DCSR5		__REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */
-#define DCSR6		__REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */
-#define DCSR7		__REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
-#define DCSR8		__REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */
-#define DCSR9		__REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */
-#define DCSR10		__REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */
-#define DCSR11		__REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
-#define DCSR12		__REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */
-#define DCSR13		__REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
-#define DCSR14		__REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
-#define DCSR15		__REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
-#ifdef CONFIG_CPU_MONAHANS
-#define DCSR16		__REG(0x40000040)  /* DMA Control / Status Register for Channel 16 */
-#define DCSR17		__REG(0x40000044)  /* DMA Control / Status Register for Channel 17 */
-#define DCSR18		__REG(0x40000048)  /* DMA Control / Status Register for Channel 18 */
-#define DCSR19		__REG(0x4000004c)  /* DMA Control / Status Register for Channel 19 */
-#define DCSR20		__REG(0x40000050)  /* DMA Control / Status Register for Channel 20 */
-#define DCSR21		__REG(0x40000054)  /* DMA Control / Status Register for Channel 21 */
-#define DCSR22		__REG(0x40000058)  /* DMA Control / Status Register for Channel 22 */
-#define DCSR23		__REG(0x4000005c)  /* DMA Control / Status Register for Channel 23 */
-#define DCSR24		__REG(0x40000060)  /* DMA Control / Status Register for Channel 24 */
-#define DCSR25		__REG(0x40000064)  /* DMA Control / Status Register for Channel 25 */
-#define DCSR26		__REG(0x40000068)  /* DMA Control / Status Register for Channel 26 */
-#define DCSR27		__REG(0x4000006c)  /* DMA Control / Status Register for Channel 27 */
-#define DCSR28		__REG(0x40000070)  /* DMA Control / Status Register for Channel 28 */
-#define DCSR29		__REG(0x40000074)  /* DMA Control / Status Register for Channel 29 */
-#define DCSR30		__REG(0x40000078)  /* DMA Control / Status Register for Channel 30 */
-#define DCSR31		__REG(0x4000007c)  /* DMA Control / Status Register for Channel 31 */
-#endif /* CONFIG_CPU_MONAHANS */
-
-#define DCSR(x)		__REG2(0x40000000, (x) << 2)
+#define DCSR0		0x40000000  /* DMA Control / Status Register for Channel 0 */
+#define DCSR1		0x40000004  /* DMA Control / Status Register for Channel 1 */
+#define DCSR2		0x40000008  /* DMA Control / Status Register for Channel 2 */
+#define DCSR3		0x4000000c  /* DMA Control / Status Register for Channel 3 */
+#define DCSR4		0x40000010  /* DMA Control / Status Register for Channel 4 */
+#define DCSR5		0x40000014  /* DMA Control / Status Register for Channel 5 */
+#define DCSR6		0x40000018  /* DMA Control / Status Register for Channel 6 */
+#define DCSR7		0x4000001c  /* DMA Control / Status Register for Channel 7 */
+#define DCSR8		0x40000020  /* DMA Control / Status Register for Channel 8 */
+#define DCSR9		0x40000024  /* DMA Control / Status Register for Channel 9 */
+#define DCSR10		0x40000028  /* DMA Control / Status Register for Channel 10 */
+#define DCSR11		0x4000002c  /* DMA Control / Status Register for Channel 11 */
+#define DCSR12		0x40000030  /* DMA Control / Status Register for Channel 12 */
+#define DCSR13		0x40000034  /* DMA Control / Status Register for Channel 13 */
+#define DCSR14		0x40000038  /* DMA Control / Status Register for Channel 14 */
+#define DCSR15		0x4000003c  /* DMA Control / Status Register for Channel 15 */
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define DCSR16		0x40000040  /* DMA Control / Status Register for Channel 16 */
+#define DCSR17		0x40000044  /* DMA Control / Status Register for Channel 17 */
+#define DCSR18		0x40000048  /* DMA Control / Status Register for Channel 18 */
+#define DCSR19		0x4000004c  /* DMA Control / Status Register for Channel 19 */
+#define DCSR20		0x40000050  /* DMA Control / Status Register for Channel 20 */
+#define DCSR21		0x40000054  /* DMA Control / Status Register for Channel 21 */
+#define DCSR22		0x40000058  /* DMA Control / Status Register for Channel 22 */
+#define DCSR23		0x4000005c  /* DMA Control / Status Register for Channel 23 */
+#define DCSR24		0x40000060  /* DMA Control / Status Register for Channel 24 */
+#define DCSR25		0x40000064  /* DMA Control / Status Register for Channel 25 */
+#define DCSR26		0x40000068  /* DMA Control / Status Register for Channel 26 */
+#define DCSR27		0x4000006c  /* DMA Control / Status Register for Channel 27 */
+#define DCSR28		0x40000070  /* DMA Control / Status Register for Channel 28 */
+#define DCSR29		0x40000074  /* DMA Control / Status Register for Channel 29 */
+#define DCSR30		0x40000078  /* DMA Control / Status Register for Channel 30 */
+#define DCSR31		0x4000007c  /* DMA Control / Status Register for Channel 31 */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+
+#define DCSR(x)		(0x40000000 | ((x) << 2))
 
 #define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
 #define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
@@ -150,52 +150,52 @@ typedef void		(*ExcpHndlr) (void) ;
 #define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
 #define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
 
-#define DINT		__REG(0x400000f0)  /* DMA Interrupt Register */
-
-#define DRCMR0		__REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
-#define DRCMR1		__REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
-#define DRCMR2		__REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
-#define DRCMR3		__REG(0x4000010c)  /* Request to Channel Map Register for I2S transmit Request */
-#define DRCMR4		__REG(0x40000110)  /* Request to Channel Map Register for BTUART receive Request */
-#define DRCMR5		__REG(0x40000114)  /* Request to Channel Map Register for BTUART transmit Request. */
-#define DRCMR6		__REG(0x40000118)  /* Request to Channel Map Register for FFUART receive Request */
-#define DRCMR7		__REG(0x4000011c)  /* Request to Channel Map Register for FFUART transmit Request */
-#define DRCMR8		__REG(0x40000120)  /* Request to Channel Map Register for AC97 microphone Request */
-#define DRCMR9		__REG(0x40000124)  /* Request to Channel Map Register for AC97 modem receive Request */
-#define DRCMR10		__REG(0x40000128)  /* Request to Channel Map Register for AC97 modem transmit Request */
-#define DRCMR11		__REG(0x4000012c)  /* Request to Channel Map Register for AC97 audio receive Request */
-#define DRCMR12		__REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */
-#define DRCMR13		__REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */
-#define DRCMR14		__REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */
-#define DRCMR15		__REG(0x4000013c)  /* Reserved */
-#define DRCMR16		__REG(0x40000140)  /* Reserved */
-#define DRCMR17		__REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */
-#define DRCMR18		__REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */
-#define DRCMR19		__REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */
-#define DRCMR20		__REG(0x40000150)  /* Request to Channel Map Register for STUART transmit Request */
-#define DRCMR21		__REG(0x40000154)  /* Request to Channel Map Register for MMC receive Request */
-#define DRCMR22		__REG(0x40000158)  /* Request to Channel Map Register for MMC transmit Request */
-#define DRCMR23		__REG(0x4000015c)  /* Reserved */
-#define DRCMR24		__REG(0x40000160)  /* Reserved */
-#define DRCMR25		__REG(0x40000164)  /* Request to Channel Map Register for USB endpoint 1 Request */
-#define DRCMR26		__REG(0x40000168)  /* Request to Channel Map Register for USB endpoint 2 Request */
-#define DRCMR27		__REG(0x4000016C)  /* Request to Channel Map Register for USB endpoint 3 Request */
-#define DRCMR28		__REG(0x40000170)  /* Request to Channel Map Register for USB endpoint 4 Request */
-#define DRCMR29		__REG(0x40000174)  /* Reserved */
-#define DRCMR30		__REG(0x40000178)  /* Request to Channel Map Register for USB endpoint 6 Request */
-#define DRCMR31		__REG(0x4000017C)  /* Request to Channel Map Register for USB endpoint 7 Request */
-#define DRCMR32		__REG(0x40000180)  /* Request to Channel Map Register for USB endpoint 8 Request */
-#define DRCMR33		__REG(0x40000184)  /* Request to Channel Map Register for USB endpoint 9 Request */
-#define DRCMR34		__REG(0x40000188)  /* Reserved */
-#define DRCMR35		__REG(0x4000018C)  /* Request to Channel Map Register for USB endpoint 11 Request */
-#define DRCMR36		__REG(0x40000190)  /* Request to Channel Map Register for USB endpoint 12 Request */
-#define DRCMR37		__REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */
-#define DRCMR38		__REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
-#define DRCMR39		__REG(0x4000019C)  /* Reserved */
-
-#define DRCMR68		       __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
-#define DRCMR69		       __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
-#define DRCMR70		       __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
+#define DINT		0x400000f0  /* DMA Interrupt Register */
+
+#define DRCMR0		0x40000100  /* Request to Channel Map Register for DREQ 0 */
+#define DRCMR1		0x40000104  /* Request to Channel Map Register for DREQ 1 */
+#define DRCMR2		0x40000108  /* Request to Channel Map Register for I2S receive Request */
+#define DRCMR3		0x4000010c  /* Request to Channel Map Register for I2S transmit Request */
+#define DRCMR4		0x40000110  /* Request to Channel Map Register for BTUART receive Request */
+#define DRCMR5		0x40000114  /* Request to Channel Map Register for BTUART transmit Request. */
+#define DRCMR6		0x40000118  /* Request to Channel Map Register for FFUART receive Request */
+#define DRCMR7		0x4000011c  /* Request to Channel Map Register for FFUART transmit Request */
+#define DRCMR8		0x40000120  /* Request to Channel Map Register for AC97 microphone Request */
+#define DRCMR9		0x40000124  /* Request to Channel Map Register for AC97 modem receive Request */
+#define DRCMR10		0x40000128  /* Request to Channel Map Register for AC97 modem transmit Request */
+#define DRCMR11		0x4000012c  /* Request to Channel Map Register for AC97 audio receive Request */
+#define DRCMR12		0x40000130  /* Request to Channel Map Register for AC97 audio transmit Request */
+#define DRCMR13		0x40000134  /* Request to Channel Map Register for SSP receive Request */
+#define DRCMR14		0x40000138  /* Request to Channel Map Register for SSP transmit Request */
+#define DRCMR15		0x4000013c  /* Reserved */
+#define DRCMR16		0x40000140  /* Reserved */
+#define DRCMR17		0x40000144  /* Request to Channel Map Register for ICP receive Request */
+#define DRCMR18		0x40000148  /* Request to Channel Map Register for ICP transmit Request */
+#define DRCMR19		0x4000014c  /* Request to Channel Map Register for STUART receive Request */
+#define DRCMR20		0x40000150  /* Request to Channel Map Register for STUART transmit Request */
+#define DRCMR21		0x40000154  /* Request to Channel Map Register for MMC receive Request */
+#define DRCMR22		0x40000158  /* Request to Channel Map Register for MMC transmit Request */
+#define DRCMR23		0x4000015c  /* Reserved */
+#define DRCMR24		0x40000160  /* Reserved */
+#define DRCMR25		0x40000164  /* Request to Channel Map Register for USB endpoint 1 Request */
+#define DRCMR26		0x40000168  /* Request to Channel Map Register for USB endpoint 2 Request */
+#define DRCMR27		0x4000016C  /* Request to Channel Map Register for USB endpoint 3 Request */
+#define DRCMR28		0x40000170  /* Request to Channel Map Register for USB endpoint 4 Request */
+#define DRCMR29		0x40000174  /* Reserved */
+#define DRCMR30		0x40000178  /* Request to Channel Map Register for USB endpoint 6 Request */
+#define DRCMR31		0x4000017C  /* Request to Channel Map Register for USB endpoint 7 Request */
+#define DRCMR32		0x40000180  /* Request to Channel Map Register for USB endpoint 8 Request */
+#define DRCMR33		0x40000184  /* Request to Channel Map Register for USB endpoint 9 Request */
+#define DRCMR34		0x40000188  /* Reserved */
+#define DRCMR35		0x4000018C  /* Request to Channel Map Register for USB endpoint 11 Request */
+#define DRCMR36		0x40000190  /* Request to Channel Map Register for USB endpoint 12 Request */
+#define DRCMR37		0x40000194  /* Request to Channel Map Register for USB endpoint 13 Request */
+#define DRCMR38		0x40000198  /* Request to Channel Map Register for USB endpoint 14 Request */
+#define DRCMR39		0x4000019C  /* Reserved */
+
+#define DRCMR68		       0x40001110  /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69		       0x40001114  /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70		       0x40001118  /* Request to Channel Map Register for Camera FIFO 2 Request */
 
 #define DRCMRRXSADR	DRCMR2
 #define DRCMRTXSADR	DRCMR3
@@ -220,75 +220,75 @@ typedef void		(*ExcpHndlr) (void) ;
 #define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
 #define DRCMR_CHLNUM	0x0f		/* mask for Channel Number (read / write) */
 
-#define DDADR0		__REG(0x40000200)  /* DMA Descriptor Address Register Channel 0 */
-#define DSADR0		__REG(0x40000204)  /* DMA Source Address Register Channel 0 */
-#define DTADR0		__REG(0x40000208)  /* DMA Target Address Register Channel 0 */
-#define DCMD0		__REG(0x4000020c)  /* DMA Command Address Register Channel 0 */
-#define DDADR1		__REG(0x40000210)  /* DMA Descriptor Address Register Channel 1 */
-#define DSADR1		__REG(0x40000214)  /* DMA Source Address Register Channel 1 */
-#define DTADR1		__REG(0x40000218)  /* DMA Target Address Register Channel 1 */
-#define DCMD1		__REG(0x4000021c)  /* DMA Command Address Register Channel 1 */
-#define DDADR2		__REG(0x40000220)  /* DMA Descriptor Address Register Channel 2 */
-#define DSADR2		__REG(0x40000224)  /* DMA Source Address Register Channel 2 */
-#define DTADR2		__REG(0x40000228)  /* DMA Target Address Register Channel 2 */
-#define DCMD2		__REG(0x4000022c)  /* DMA Command Address Register Channel 2 */
-#define DDADR3		__REG(0x40000230)  /* DMA Descriptor Address Register Channel 3 */
-#define DSADR3		__REG(0x40000234)  /* DMA Source Address Register Channel 3 */
-#define DTADR3		__REG(0x40000238)  /* DMA Target Address Register Channel 3 */
-#define DCMD3		__REG(0x4000023c)  /* DMA Command Address Register Channel 3 */
-#define DDADR4		__REG(0x40000240)  /* DMA Descriptor Address Register Channel 4 */
-#define DSADR4		__REG(0x40000244)  /* DMA Source Address Register Channel 4 */
-#define DTADR4		__REG(0x40000248)  /* DMA Target Address Register Channel 4 */
-#define DCMD4		__REG(0x4000024c)  /* DMA Command Address Register Channel 4 */
-#define DDADR5		__REG(0x40000250)  /* DMA Descriptor Address Register Channel 5 */
-#define DSADR5		__REG(0x40000254)  /* DMA Source Address Register Channel 5 */
-#define DTADR5		__REG(0x40000258)  /* DMA Target Address Register Channel 5 */
-#define DCMD5		__REG(0x4000025c)  /* DMA Command Address Register Channel 5 */
-#define DDADR6		__REG(0x40000260)  /* DMA Descriptor Address Register Channel 6 */
-#define DSADR6		__REG(0x40000264)  /* DMA Source Address Register Channel 6 */
-#define DTADR6		__REG(0x40000268)  /* DMA Target Address Register Channel 6 */
-#define DCMD6		__REG(0x4000026c)  /* DMA Command Address Register Channel 6 */
-#define DDADR7		__REG(0x40000270)  /* DMA Descriptor Address Register Channel 7 */
-#define DSADR7		__REG(0x40000274)  /* DMA Source Address Register Channel 7 */
-#define DTADR7		__REG(0x40000278)  /* DMA Target Address Register Channel 7 */
-#define DCMD7		__REG(0x4000027c)  /* DMA Command Address Register Channel 7 */
-#define DDADR8		__REG(0x40000280)  /* DMA Descriptor Address Register Channel 8 */
-#define DSADR8		__REG(0x40000284)  /* DMA Source Address Register Channel 8 */
-#define DTADR8		__REG(0x40000288)  /* DMA Target Address Register Channel 8 */
-#define DCMD8		__REG(0x4000028c)  /* DMA Command Address Register Channel 8 */
-#define DDADR9		__REG(0x40000290)  /* DMA Descriptor Address Register Channel 9 */
-#define DSADR9		__REG(0x40000294)  /* DMA Source Address Register Channel 9 */
-#define DTADR9		__REG(0x40000298)  /* DMA Target Address Register Channel 9 */
-#define DCMD9		__REG(0x4000029c)  /* DMA Command Address Register Channel 9 */
-#define DDADR10		__REG(0x400002a0)  /* DMA Descriptor Address Register Channel 10 */
-#define DSADR10		__REG(0x400002a4)  /* DMA Source Address Register Channel 10 */
-#define DTADR10		__REG(0x400002a8)  /* DMA Target Address Register Channel 10 */
-#define DCMD10		__REG(0x400002ac)  /* DMA Command Address Register Channel 10 */
-#define DDADR11		__REG(0x400002b0)  /* DMA Descriptor Address Register Channel 11 */
-#define DSADR11		__REG(0x400002b4)  /* DMA Source Address Register Channel 11 */
-#define DTADR11		__REG(0x400002b8)  /* DMA Target Address Register Channel 11 */
-#define DCMD11		__REG(0x400002bc)  /* DMA Command Address Register Channel 11 */
-#define DDADR12		__REG(0x400002c0)  /* DMA Descriptor Address Register Channel 12 */
-#define DSADR12		__REG(0x400002c4)  /* DMA Source Address Register Channel 12 */
-#define DTADR12		__REG(0x400002c8)  /* DMA Target Address Register Channel 12 */
-#define DCMD12		__REG(0x400002cc)  /* DMA Command Address Register Channel 12 */
-#define DDADR13		__REG(0x400002d0)  /* DMA Descriptor Address Register Channel 13 */
-#define DSADR13		__REG(0x400002d4)  /* DMA Source Address Register Channel 13 */
-#define DTADR13		__REG(0x400002d8)  /* DMA Target Address Register Channel 13 */
-#define DCMD13		__REG(0x400002dc)  /* DMA Command Address Register Channel 13 */
-#define DDADR14		__REG(0x400002e0)  /* DMA Descriptor Address Register Channel 14 */
-#define DSADR14		__REG(0x400002e4)  /* DMA Source Address Register Channel 14 */
-#define DTADR14		__REG(0x400002e8)  /* DMA Target Address Register Channel 14 */
-#define DCMD14		__REG(0x400002ec)  /* DMA Command Address Register Channel 14 */
-#define DDADR15		__REG(0x400002f0)  /* DMA Descriptor Address Register Channel 15 */
-#define DSADR15		__REG(0x400002f4)  /* DMA Source Address Register Channel 15 */
-#define DTADR15		__REG(0x400002f8)  /* DMA Target Address Register Channel 15 */
-#define DCMD15		__REG(0x400002fc)  /* DMA Command Address Register Channel 15 */
-
-#define DDADR(x)	__REG2(0x40000200, (x) << 4)
-#define DSADR(x)	__REG2(0x40000204, (x) << 4)
-#define DTADR(x)	__REG2(0x40000208, (x) << 4)
-#define DCMD(x)		__REG2(0x4000020c, (x) << 4)
+#define DDADR0		0x40000200  /* DMA Descriptor Address Register Channel 0 */
+#define DSADR0		0x40000204  /* DMA Source Address Register Channel 0 */
+#define DTADR0		0x40000208  /* DMA Target Address Register Channel 0 */
+#define DCMD0		0x4000020c  /* DMA Command Address Register Channel 0 */
+#define DDADR1		0x40000210  /* DMA Descriptor Address Register Channel 1 */
+#define DSADR1		0x40000214  /* DMA Source Address Register Channel 1 */
+#define DTADR1		0x40000218  /* DMA Target Address Register Channel 1 */
+#define DCMD1		0x4000021c  /* DMA Command Address Register Channel 1 */
+#define DDADR2		0x40000220  /* DMA Descriptor Address Register Channel 2 */
+#define DSADR2		0x40000224  /* DMA Source Address Register Channel 2 */
+#define DTADR2		0x40000228  /* DMA Target Address Register Channel 2 */
+#define DCMD2		0x4000022c  /* DMA Command Address Register Channel 2 */
+#define DDADR3		0x40000230  /* DMA Descriptor Address Register Channel 3 */
+#define DSADR3		0x40000234  /* DMA Source Address Register Channel 3 */
+#define DTADR3		0x40000238  /* DMA Target Address Register Channel 3 */
+#define DCMD3		0x4000023c  /* DMA Command Address Register Channel 3 */
+#define DDADR4		0x40000240  /* DMA Descriptor Address Register Channel 4 */
+#define DSADR4		0x40000244  /* DMA Source Address Register Channel 4 */
+#define DTADR4		0x40000248  /* DMA Target Address Register Channel 4 */
+#define DCMD4		0x4000024c  /* DMA Command Address Register Channel 4 */
+#define DDADR5		0x40000250  /* DMA Descriptor Address Register Channel 5 */
+#define DSADR5		0x40000254  /* DMA Source Address Register Channel 5 */
+#define DTADR5		0x40000258  /* DMA Target Address Register Channel 5 */
+#define DCMD5		0x4000025c  /* DMA Command Address Register Channel 5 */
+#define DDADR6		0x40000260  /* DMA Descriptor Address Register Channel 6 */
+#define DSADR6		0x40000264  /* DMA Source Address Register Channel 6 */
+#define DTADR6		0x40000268  /* DMA Target Address Register Channel 6 */
+#define DCMD6		0x4000026c  /* DMA Command Address Register Channel 6 */
+#define DDADR7		0x40000270  /* DMA Descriptor Address Register Channel 7 */
+#define DSADR7		0x40000274  /* DMA Source Address Register Channel 7 */
+#define DTADR7		0x40000278  /* DMA Target Address Register Channel 7 */
+#define DCMD7		0x4000027c  /* DMA Command Address Register Channel 7 */
+#define DDADR8		0x40000280  /* DMA Descriptor Address Register Channel 8 */
+#define DSADR8		0x40000284  /* DMA Source Address Register Channel 8 */
+#define DTADR8		0x40000288  /* DMA Target Address Register Channel 8 */
+#define DCMD8		0x4000028c  /* DMA Command Address Register Channel 8 */
+#define DDADR9		0x40000290  /* DMA Descriptor Address Register Channel 9 */
+#define DSADR9		0x40000294  /* DMA Source Address Register Channel 9 */
+#define DTADR9		0x40000298  /* DMA Target Address Register Channel 9 */
+#define DCMD9		0x4000029c  /* DMA Command Address Register Channel 9 */
+#define DDADR10		0x400002a0  /* DMA Descriptor Address Register Channel 10 */
+#define DSADR10		0x400002a4  /* DMA Source Address Register Channel 10 */
+#define DTADR10		0x400002a8  /* DMA Target Address Register Channel 10 */
+#define DCMD10		0x400002ac  /* DMA Command Address Register Channel 10 */
+#define DDADR11		0x400002b0  /* DMA Descriptor Address Register Channel 11 */
+#define DSADR11		0x400002b4  /* DMA Source Address Register Channel 11 */
+#define DTADR11		0x400002b8  /* DMA Target Address Register Channel 11 */
+#define DCMD11		0x400002bc  /* DMA Command Address Register Channel 11 */
+#define DDADR12		0x400002c0  /* DMA Descriptor Address Register Channel 12 */
+#define DSADR12		0x400002c4  /* DMA Source Address Register Channel 12 */
+#define DTADR12		0x400002c8  /* DMA Target Address Register Channel 12 */
+#define DCMD12		0x400002cc  /* DMA Command Address Register Channel 12 */
+#define DDADR13		0x400002d0  /* DMA Descriptor Address Register Channel 13 */
+#define DSADR13		0x400002d4  /* DMA Source Address Register Channel 13 */
+#define DTADR13		0x400002d8  /* DMA Target Address Register Channel 13 */
+#define DCMD13		0x400002dc  /* DMA Command Address Register Channel 13 */
+#define DDADR14		0x400002e0  /* DMA Descriptor Address Register Channel 14 */
+#define DSADR14		0x400002e4  /* DMA Source Address Register Channel 14 */
+#define DTADR14		0x400002e8  /* DMA Target Address Register Channel 14 */
+#define DCMD14		0x400002ec  /* DMA Command Address Register Channel 14 */
+#define DDADR15		0x400002f0  /* DMA Descriptor Address Register Channel 15 */
+#define DSADR15		0x400002f4  /* DMA Source Address Register Channel 15 */
+#define DTADR15		0x400002f8  /* DMA Target Address Register Channel 15 */
+#define DCMD15		0x400002fc  /* DMA Command Address Register Channel 15 */
+
+#define DDADR(x)	(0x40000200 | ((x) << 4))
+#define DSADR(x)	(0x40000204 | ((x) << 4))
+#define DTADR(x)	(0x40000208 | ((x) << 4))
+#define DCMD(x)		(0x4000020c | ((x) << 4))
 
 #define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
 #define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
@@ -313,56 +313,57 @@ typedef void		(*ExcpHndlr) (void) ;
 #define DCMD_RXMCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
 #define DCMD_TXPCDR	(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
 
+/******************************************************************************/
 /*
  * UARTs
  */
 /* Full Function UART (FFUART) */
 #define FFUART		FFRBR
-#define FFRBR		__REG(0x40100000)  /* Receive Buffer Register (read only) */
-#define FFTHR		__REG(0x40100000)  /* Transmit Holding Register (write only) */
-#define FFIER		__REG(0x40100004)  /* Interrupt Enable Register (read/write) */
-#define FFIIR		__REG(0x40100008)  /* Interrupt ID Register (read only) */
-#define FFFCR		__REG(0x40100008)  /* FIFO Control Register (write only) */
-#define FFLCR		__REG(0x4010000C)  /* Line Control Register (read/write) */
-#define FFMCR		__REG(0x40100010)  /* Modem Control Register (read/write) */
-#define FFLSR		__REG(0x40100014)  /* Line Status Register (read only) */
-#define FFMSR		__REG(0x40100018)  /* Modem Status Register (read only) */
-#define FFSPR		__REG(0x4010001C)  /* Scratch Pad Register (read/write) */
-#define FFISR		__REG(0x40100020)  /* Infrared Selection Register (read/write) */
-#define FFDLL		__REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define FFDLH		__REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define FFRBR		0x40100000  /* Receive Buffer Register (read only) */
+#define FFTHR		0x40100000  /* Transmit Holding Register (write only) */
+#define FFIER		0x40100004  /* Interrupt Enable Register (read/write) */
+#define FFIIR		0x40100008  /* Interrupt ID Register (read only) */
+#define FFFCR		0x40100008  /* FIFO Control Register (write only) */
+#define FFLCR		0x4010000C  /* Line Control Register (read/write) */
+#define FFMCR		0x40100010  /* Modem Control Register (read/write) */
+#define FFLSR		0x40100014  /* Line Status Register (read only) */
+#define FFMSR		0x40100018  /* Modem Status Register (read only) */
+#define FFSPR		0x4010001C  /* Scratch Pad Register (read/write) */
+#define FFISR		0x40100020  /* Infrared Selection Register (read/write) */
+#define FFDLL		0x40100000  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define FFDLH		0x40100004  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 
 /* Bluetooth UART (BTUART) */
 #define BTUART		BTRBR
-#define BTRBR		__REG(0x40200000)  /* Receive Buffer Register (read only) */
-#define BTTHR		__REG(0x40200000)  /* Transmit Holding Register (write only) */
-#define BTIER		__REG(0x40200004)  /* Interrupt Enable Register (read/write) */
-#define BTIIR		__REG(0x40200008)  /* Interrupt ID Register (read only) */
-#define BTFCR		__REG(0x40200008)  /* FIFO Control Register (write only) */
-#define BTLCR		__REG(0x4020000C)  /* Line Control Register (read/write) */
-#define BTMCR		__REG(0x40200010)  /* Modem Control Register (read/write) */
-#define BTLSR		__REG(0x40200014)  /* Line Status Register (read only) */
-#define BTMSR		__REG(0x40200018)  /* Modem Status Register (read only) */
-#define BTSPR		__REG(0x4020001C)  /* Scratch Pad Register (read/write) */
-#define BTISR		__REG(0x40200020)  /* Infrared Selection Register (read/write) */
-#define BTDLL		__REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define BTDLH		__REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define BTRBR		0x40200000  /* Receive Buffer Register (read only) */
+#define BTTHR		0x40200000  /* Transmit Holding Register (write only) */
+#define BTIER		0x40200004  /* Interrupt Enable Register (read/write) */
+#define BTIIR		0x40200008  /* Interrupt ID Register (read only) */
+#define BTFCR		0x40200008  /* FIFO Control Register (write only) */
+#define BTLCR		0x4020000C  /* Line Control Register (read/write) */
+#define BTMCR		0x40200010  /* Modem Control Register (read/write) */
+#define BTLSR		0x40200014  /* Line Status Register (read only) */
+#define BTMSR		0x40200018  /* Modem Status Register (read only) */
+#define BTSPR		0x4020001C  /* Scratch Pad Register (read/write) */
+#define BTISR		0x40200020  /* Infrared Selection Register (read/write) */
+#define BTDLL		0x40200000  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define BTDLH		0x40200004  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 
 /* Standard UART (STUART) */
 #define STUART		STRBR
-#define STRBR		__REG(0x40700000)  /* Receive Buffer Register (read only) */
-#define STTHR		__REG(0x40700000)  /* Transmit Holding Register (write only) */
-#define STIER		__REG(0x40700004)  /* Interrupt Enable Register (read/write) */
-#define STIIR		__REG(0x40700008)  /* Interrupt ID Register (read only) */
-#define STFCR		__REG(0x40700008)  /* FIFO Control Register (write only) */
-#define STLCR		__REG(0x4070000C)  /* Line Control Register (read/write) */
-#define STMCR		__REG(0x40700010)  /* Modem Control Register (read/write) */
-#define STLSR		__REG(0x40700014)  /* Line Status Register (read only) */
-#define STMSR		__REG(0x40700018)  /* Reserved */
-#define STSPR		__REG(0x4070001C)  /* Scratch Pad Register (read/write) */
-#define STISR		__REG(0x40700020)  /* Infrared Selection Register (read/write) */
-#define STDLL		__REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define STDLH		__REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define STRBR		0x40700000  /* Receive Buffer Register (read only) */
+#define STTHR		0x40700000  /* Transmit Holding Register (write only) */
+#define STIER		0x40700004  /* Interrupt Enable Register (read/write) */
+#define STIIR		0x40700008  /* Interrupt ID Register (read only) */
+#define STFCR		0x40700008  /* FIFO Control Register (write only) */
+#define STLCR		0x4070000C  /* Line Control Register (read/write) */
+#define STMCR		0x40700010  /* Modem Control Register (read/write) */
+#define STLSR		0x40700014  /* Line Status Register (read only) */
+#define STMSR		0x40700018  /* Reserved */
+#define STSPR		0x4070001C  /* Scratch Pad Register (read/write) */
+#define STISR		0x40700020  /* Infrared Selection Register (read/write) */
+#define STDLL		0x40700000  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define STDLH		0x40700004  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 
 #define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
 #define IER_UUE		(1 << 6)	/* UART Unit Enable */
@@ -408,7 +409,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define LSR_OE		(1 << 1)	/* Overrun Error */
 #define LSR_DR		(1 << 0)	/* Data Ready */
 
-#define MCR_LOOP	(1 << 4)	*/
+#define MCR_LOOP	(1 << 4)	/* */
 #define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
 #define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
 #define MCR_RTS		(1 << 1)	/* Request to Send */
@@ -423,6 +424,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
 #define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
 
+/******************************************************************************/
 /*
  * IrSR (Infrared Selection Register)
  */
@@ -456,17 +458,25 @@ typedef void		(*ExcpHndlr) (void) ;
 /*
  * I2C registers
  */
-#define IBMR		__REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */
-#define IDBR		__REG(0x40301688)  /* I2C Data Buffer Register - IDBR */
-#define ICR		__REG(0x40301690)  /* I2C Control Register - ICR */
-#define ISR		__REG(0x40301698)  /* I2C Status Register - ISR */
-#define ISAR		__REG(0x403016A0)  /* I2C Slave Address Register - ISAR */
-
-#define PWRIBMR		__REG(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */
-#define PWRIDBR		__REG(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */
-#define PWRICR		__REG(0x40f00190)  /* Power I2C Control Register - ICR */
-#define PWRISR		__REG(0x40f00198)  /* Power I2C Status Register - ISR */
-#define PWRISAR		__REG(0x40f001A0)  /* Power I2C Slave Address Register-ISAR */
+#define IBMR		0x40301680  /* I2C Bus Monitor Register - IBMR */
+#define IDBR		0x40301688  /* I2C Data Buffer Register - IDBR */
+#define ICR		0x40301690  /* I2C Control Register - ICR */
+#define ISR		0x40301698  /* I2C Status Register - ISR */
+#define ISAR		0x403016A0  /* I2C Slave Address Register - ISAR */
+
+#ifdef CONFIG_CPU_MONAHANS
+#define PWRIBMR		0x40f500C0  /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR		0x40f500C4  /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR		0x40f500C8  /* Power I2C Control Register - ICR */
+#define PWRISR		0x40f500CC  /* Power I2C Status Register - ISR */
+#define PWRISAR		0x40f500D0  /* Power I2C Slave Address Register-ISAR */
+#else
+#define PWRIBMR		0x40f00180  /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR		0x40f00188  /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR		0x40f00190  /* Power I2C Control Register - ICR */
+#define PWRISR		0x40f00198  /* Power I2C Status Register - ISR */
+#define PWRISAR		0x40f001A0  /* Power I2C Slave Address Register-ISAR */
+#endif
 
 /* ----- Control register bits ---------------------------------------- */
 
@@ -507,28 +517,27 @@ typedef void		(*ExcpHndlr) (void) ;
 /* FIXME the audio defines collide w/ the SA1111 defines.  I don't like these
  * short defines because there is too much chance of namespace collision
  */
-/*#define SACR0		__REG(0x40400000)  /  Global Control Register */
-/*#define SACR1		__REG(0x40400004)  /  Serial Audio I 2 S/MSB-Justified Control Register */
-/*#define SASR0		__REG(0x4040000C)  /  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
-/*#define SAIMR		__REG(0x40400014)  /  Serial Audio Interrupt Mask Register */
-/*#define SAICR		__REG(0x40400018)  /  Serial Audio Interrupt Clear Register */
-/*#define SADIV		__REG(0x40400060)  /  Audio Clock Divider Register. */
-/*#define SADR		__REG(0x40400080)  /  Serial Audio Data Register (TX and RX FIFO access Register). */
-
+#define SACR0		0x40400000  /*  Global Control Register */
+#define SACR1		0x40400004  /*  Serial Audio I 2 S/MSB-Justified Control Register */
+#define SASR0		0x4040000C  /*  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+#define SAIMR		0x40400014  /*  Serial Audio Interrupt Mask Register */
+#define SAICR		0x40400018  /*  Serial Audio Interrupt Clear Register */
+#define SADIV		0x40400060  /*  Audio Clock Divider Register. */
+#define SADR		0x40400080  /*  Serial Audio Data Register (TX and RX FIFO access Register). */
 
 /*
  * AC97 Controller registers
  */
-#define POCR		__REG(0x40500000)  /* PCM Out Control Register */
+#define POCR		0x40500000  /* PCM Out Control Register */
 #define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 
-#define PICR		__REG(0x40500004)  /* PCM In Control Register */
+#define PICR		0x40500004  /* PCM In Control Register */
 #define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 
-#define MCCR		__REG(0x40500008)  /* Mic In Control Register */
+#define MCCR		0x40500008  /* Mic In Control Register */
 #define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 
-#define GCR		__REG(0x4050000C)  /* Global Control Register */
+#define GCR		0x4050000C  /* Global Control Register */
 #define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
 #define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
 #define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
@@ -540,16 +549,16 @@ typedef void		(*ExcpHndlr) (void) ;
 #define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
 #define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */
 
-#define POSR		__REG(0x40500010)  /* PCM Out Status Register */
+#define POSR		0x40500010  /* PCM Out Status Register */
 #define POSR_FIFOE	(1 << 4)	/* FIFO error */
 
-#define PISR		__REG(0x40500014)  /* PCM In Status Register */
+#define PISR		0x40500014  /* PCM In Status Register */
 #define PISR_FIFOE	(1 << 4)	/* FIFO error */
 
-#define MCSR		__REG(0x40500018)  /* Mic In Status Register */
+#define MCSR		0x40500018  /* Mic In Status Register */
 #define MCSR_FIFOE	(1 << 4)	/* FIFO error */
 
-#define GSR		__REG(0x4050001C)  /* Global Status Register */
+#define GSR		0x4050001C  /* Global Status Register */
 #define GSR_CDONE	(1 << 19)	/* Command Done */
 #define GSR_SDONE	(1 << 18)	/* Status Done */
 #define GSR_RDCS	(1 << 15)	/* Read Completion Status */
@@ -567,38 +576,38 @@ typedef void		(*ExcpHndlr) (void) ;
 #define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
 #define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */
 
-#define CAR		__REG(0x40500020)  /* CODEC Access Register */
+#define CAR		0x40500020  /* CODEC Access Register */
 #define CAR_CAIP	(1 << 0)	/* Codec Access In Progress */
 
-#define PCDR		__REG(0x40500040)  /* PCM FIFO Data Register */
-#define MCDR		__REG(0x40500060)  /* Mic-in FIFO Data Register */
+#define PCDR		0x40500040  /* PCM FIFO Data Register */
+#define MCDR		0x40500060  /* Mic-in FIFO Data Register */
 
-#define MOCR		__REG(0x40500100)  /* Modem Out Control Register */
+#define MOCR		0x40500100  /* Modem Out Control Register */
 #define MOCR_FEIE	(1 << 3)	/* FIFO Error */
 
-#define MICR		__REG(0x40500108)  /* Modem In Control Register */
+#define MICR		0x40500108  /* Modem In Control Register */
 #define MICR_FEIE	(1 << 3)	/* FIFO Error */
 
-#define MOSR		__REG(0x40500110)  /* Modem Out Status Register */
+#define MOSR		0x40500110  /* Modem Out Status Register */
 #define MOSR_FIFOE	(1 << 4)	/* FIFO error */
 
-#define MISR		__REG(0x40500118)  /* Modem In Status Register */
+#define MISR		0x40500118  /* Modem In Status Register */
 #define MISR_FIFOE	(1 << 4)	/* FIFO error */
 
-#define MODR		__REG(0x40500140)  /* Modem FIFO Data Register */
+#define MODR		0x40500140  /* Modem FIFO Data Register */
 
-#define PAC_REG_BASE	__REG(0x40500200)  /* Primary Audio Codec */
-#define SAC_REG_BASE	__REG(0x40500300)  /* Secondary Audio Codec */
-#define PMC_REG_BASE	__REG(0x40500400)  /* Primary Modem Codec */
-#define SMC_REG_BASE	__REG(0x40500500)  /* Secondary Modem Codec */
+#define PAC_REG_BASE	0x40500200  /* Primary Audio Codec */
+#define SAC_REG_BASE	0x40500300  /* Secondary Audio Codec */
+#define PMC_REG_BASE	0x40500400  /* Primary Modem Codec */
+#define SMC_REG_BASE	0x40500500  /* Secondary Modem Codec */
 
 
 /*
  * USB Device Controller
  */
-#ifdef CONFIG_PXA27X
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 
-#define UDCCR		__REG(0x40600000)	/* UDC Control Register */
+#define UDCCR		0x40600000	/* UDC Control Register */
 #define UDCCR_UDE	(1 << 0)		/* UDC enable */
 #define UDCCR_UDA	(1 << 1)		/* UDC active */
 #define UDCCR_RSM	(1 << 2)		/* Device resume */
@@ -623,7 +632,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCR_AAISN	(0x07 << 5)		/* Active UDC Alternate Interface  Setting Number */
 #define UDCCR_AAISN_S	5
 
-#define UDCCS0		__REG(0x40600100)	/* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0		0x40600100	/* UDC Endpoint 0 Control/Status Register */
 #define UDCCS0_OPR	(1 << 0)		/* OUT packet ready */
 #define UDCCS0_IPR	(1 << 1)		/* IN packet ready */
 #define UDCCS0_FTF	(1 << 2)		/* Flush Tx FIFO */
@@ -634,9 +643,9 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCS0_SA	(1 << 7)		/* Setup active */
 
 /* Bulk IN - Endpoint 1,6,11 */
-#define UDCCS1		__REG(0x40600104)  /* UDC Endpoint 1 (IN) Control/Status Register */
-#define UDCCS6		__REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
-#define UDCCS11		__REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
+#define UDCCS1		0x40600104  /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6		0x40600028  /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11		0x4060003C  /* UDC Endpoint 11 (IN) Control/Status Register */
 
 #define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
 #define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
@@ -647,9 +656,9 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
 
 /* Bulk OUT - Endpoint 2,7,12 */
-#define UDCCS2		__REG(0x40600108)  /* UDC Endpoint 2 (OUT) Control/Status Register */
-#define UDCCS7		__REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
-#define UDCCS12		__REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
+#define UDCCS2		0x40600108  /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7		0x4060002C  /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12		0x40600040  /* UDC Endpoint 12 (OUT) Control/Status Register */
 
 #define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
 #define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
@@ -660,9 +669,9 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
 
 /* Isochronous IN - Endpoint 3,8,13 */
-#define UDCCS3		__REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
-#define UDCCS8		__REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
-#define UDCCS13		__REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
+#define UDCCS3		0x4060001C  /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8		0x40600030  /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13		0x40600044  /* UDC Endpoint 13 (IN) Control/Status Register */
 
 #define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
 #define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
@@ -671,9 +680,9 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
 
 /* Isochronous OUT - Endpoint 4,9,14 */
-#define UDCCS4		__REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
-#define UDCCS9		__REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
-#define UDCCS14		__REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
+#define UDCCS4		0x40600020  /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9		0x40600034  /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14		0x40600048  /* UDC Endpoint 14 (OUT) Control/Status Register */
 
 #define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
 #define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
@@ -683,9 +692,9 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
 
 /* Interrupt IN - Endpoint 5,10,15 */
-#define UDCCS5		__REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
-#define UDCCS10		__REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
-#define UDCCS15		__REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+#define UDCCS5		0x40600024  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10		0x40600038  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15		0x4060004C  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
 
 #define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
 #define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
@@ -695,32 +704,32 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCS_INT_FST	(1 << 5)	/* Force stall */
 #define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
 
-#define UFNRH		__REG(0x40600060)  /* UDC Frame Number Register High */
-#define UFNRL		__REG(0x40600014)  /* UDC Frame Number Register Low */
-#define UBCR2		__REG(0x40600208)  /* UDC Byte Count Reg 2 */
-#define UBCR4		__REG(0x4060006c)  /* UDC Byte Count Reg 4 */
-#define UBCR7		__REG(0x40600070)  /* UDC Byte Count Reg 7 */
-#define UBCR9		__REG(0x40600074)  /* UDC Byte Count Reg 9 */
-#define UBCR12		__REG(0x40600078)  /* UDC Byte Count Reg 12 */
-#define UBCR14		__REG(0x4060007c)  /* UDC Byte Count Reg 14 */
-#define UDDR0		__REG(0x40600300)  /* UDC Endpoint 0 Data Register */
-#define UDDR1		__REG(0x40600304)  /* UDC Endpoint 1 Data Register */
-#define UDDR2		__REG(0x40600308)  /* UDC Endpoint 2 Data Register */
-#define UDDR3		__REG(0x40600200)  /* UDC Endpoint 3 Data Register */
-#define UDDR4		__REG(0x40600400)  /* UDC Endpoint 4 Data Register */
-#define UDDR5		__REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
-#define UDDR6		__REG(0x40600600)  /* UDC Endpoint 6 Data Register */
-#define UDDR7		__REG(0x40600680)  /* UDC Endpoint 7 Data Register */
-#define UDDR8		__REG(0x40600700)  /* UDC Endpoint 8 Data Register */
-#define UDDR9		__REG(0x40600900)  /* UDC Endpoint 9 Data Register */
-#define UDDR10		__REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
-#define UDDR11		__REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
-#define UDDR12		__REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
-#define UDDR13		__REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
-#define UDDR14		__REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
-#define UDDR15		__REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
-
-#define UICR0		__REG(0x40600004)  /* UDC Interrupt Control Register 0 */
+#define UFNRH		0x40600060  /* UDC Frame Number Register High */
+#define UFNRL		0x40600014  /* UDC Frame Number Register Low */
+#define UBCR2		0x40600208  /* UDC Byte Count Reg 2 */
+#define UBCR4		0x4060006c  /* UDC Byte Count Reg 4 */
+#define UBCR7		0x40600070  /* UDC Byte Count Reg 7 */
+#define UBCR9		0x40600074  /* UDC Byte Count Reg 9 */
+#define UBCR12		0x40600078  /* UDC Byte Count Reg 12 */
+#define UBCR14		0x4060007c  /* UDC Byte Count Reg 14 */
+#define UDDR0		0x40600300  /* UDC Endpoint 0 Data Register */
+#define UDDR1		0x40600304  /* UDC Endpoint 1 Data Register */
+#define UDDR2		0x40600308  /* UDC Endpoint 2 Data Register */
+#define UDDR3		0x40600200  /* UDC Endpoint 3 Data Register */
+#define UDDR4		0x40600400  /* UDC Endpoint 4 Data Register */
+#define UDDR5		0x406000A0  /* UDC Endpoint 5 Data Register */
+#define UDDR6		0x40600600  /* UDC Endpoint 6 Data Register */
+#define UDDR7		0x40600680  /* UDC Endpoint 7 Data Register */
+#define UDDR8		0x40600700  /* UDC Endpoint 8 Data Register */
+#define UDDR9		0x40600900  /* UDC Endpoint 9 Data Register */
+#define UDDR10		0x406000C0  /* UDC Endpoint 10 Data Register */
+#define UDDR11		0x40600B00  /* UDC Endpoint 11 Data Register */
+#define UDDR12		0x40600B80  /* UDC Endpoint 12 Data Register */
+#define UDDR13		0x40600C00  /* UDC Endpoint 13 Data Register */
+#define UDDR14		0x40600E00  /* UDC Endpoint 14 Data Register */
+#define UDDR15		0x406000E0  /* UDC Endpoint 15 Data Register */
+
+#define UICR0		0x40600004  /* UDC Interrupt Control Register 0 */
 
 #define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
 #define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
@@ -731,7 +740,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
 #define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
 
-#define UICR1		__REG(0x40600008)  /* UDC Interrupt Control Register 1 */
+#define UICR1		0x40600008  /* UDC Interrupt Control Register 1 */
 
 #define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
 #define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
@@ -742,7 +751,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
 #define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
 
-#define USIR0		__REG(0x4060000C)  /* UDC Status Interrupt Register 0 */
+#define USIR0		0x4060000C  /* UDC Status Interrupt Register 0 */
 
 #define USIR0_IR0	(1 << 0)	/* Interrup request ep 0 */
 #define USIR0_IR1	(1 << 2)	/* Interrup request ep 1 */
@@ -753,7 +762,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define USIR0_IR6	(1 << 6)	/* Interrup request ep 6 */
 #define USIR0_IR7	(1 << 7)	/* Interrup request ep 7 */
 
-#define USIR1		__REG(0x40600010)  /* UDC Status Interrupt Register 1 */
+#define USIR1		0x40600010  /* UDC Status Interrupt Register 1 */
 
 #define USIR1_IR8	(1 << 0)	/* Interrup request ep 8 */
 #define USIR1_IR9	(1 << 1)	/* Interrup request ep 9 */
@@ -765,8 +774,8 @@ typedef void		(*ExcpHndlr) (void) ;
 #define USIR1_IR15	(1 << 7)	/* Interrup request ep 15 */
 
 
-#define UDCICR0         __REG(0x40600004)	/* UDC Interrupt Control Register0 */
-#define UDCICR1         __REG(0x40600008)	/* UDC Interrupt Control Register1 */
+#define UDCICR0         0x40600004	/* UDC Interrupt Control Register0 */
+#define UDCICR1         0x40600008	/* UDC Interrupt Control Register1 */
 #define UDCICR_FIFOERR	(1 << 1)			/* FIFO Error interrupt for EP */
 #define UDCICR_PKTCOMPL (1 << 0)			/* Packet Complete interrupt for EP */
 
@@ -777,8 +786,8 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCICR1_IESU	(1 << 28)	/* IntEn - Suspend */
 #define UDCICR1_IERS	(1 << 27)	/* IntEn - Reset */
 
-#define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
-#define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
+#define UDCISR0         0x4060000C /* UDC Interrupt Status Register 0 */
+#define UDCISR1         0x40600010 /* UDC Interrupt Status Register 1 */
 #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
 #define UDCISR1_IRCC	(1 << 31)	/* IntEn - Configuration Change */
 #define UDCISR1_IRSOF	(1 << 30)	/* IntEn - Start of Frame */
@@ -787,8 +796,8 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCISR1_IRRS	(1 << 27)	/* IntEn - Reset */
 
 
-#define UDCFNR			__REG(0x40600014) /* UDC Frame Number Register */
-#define UDCOTGICR		__REG(0x40600018) /* UDC On-The-Go interrupt control */
+#define UDCFNR			0x40600014 /* UDC Frame Number Register */
+#define UDCOTGICR		0x40600018 /* UDC On-The-Go interrupt control */
 #define UDCOTGICR_IESF		(1 << 24)	/* OTG SET_FEATURE command recvd */
 #define UDCOTGICR_IEXR		(1 << 17)	/* Extra Transciever Interrupt Rising Edge Interrupt Enable */
 #define UDCOTGICR_IEXF		(1 << 16)	/* Extra Transciever Interrupt Falling Edge Interrupt Enable */
@@ -804,7 +813,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCOTGICR_IEIDF		(1 << 0)	/* OTG ID Change Falling Edge Interrupt Enable */
 
 #define UDCCSN(x)	__REG2(0x40600100, (x) << 2)
-#define UDCCSR0		__REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
+#define UDCCSR0		0x40600100 /* UDC Control/Status register - Endpoint 0 */
 
 #define UDCCSR0_SA	(1 << 7)	/* Setup Active */
 #define UDCCSR0_RNE	(1 << 6)	/* Receive FIFO Not Empty */
@@ -815,29 +824,29 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCSR0_IPR	(1 << 1)	/* IN Packet Ready */
 #define UDCCSR0_OPC	(1 << 0)	/* OUT Packet Complete */
 
-#define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
-#define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
-#define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
-#define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
-#define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
-#define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
-#define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
-#define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
-#define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
-#define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
-#define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
-#define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
-#define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
-#define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
-#define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
-#define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
-#define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
-#define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
-#define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
-#define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
-#define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
-#define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
-#define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
+#define UDCCSRA         0x40600104 /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB         0x40600108 /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC         0x4060010C /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD         0x40600110 /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE         0x40600114 /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF         0x40600118 /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG         0x4060011C /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH         0x40600120 /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI         0x40600124 /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ         0x40600128 /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK         0x4060012C /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL         0x40600130 /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM         0x40600134 /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN         0x40600138 /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP         0x4060013C /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ         0x40600140 /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR         0x40600144 /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS         0x40600148 /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT         0x4060014C /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU         0x40600150 /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV         0x40600154 /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW         0x40600158 /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX         0x4060015C /* UDC Control/Status register - Endpoint X */
 
 #define UDCCSR_DPE	(1 << 9)	/* Data Packet Error */
 #define UDCCSR_FEF	(1 << 8)	/* Flush Endpoint FIFO */
@@ -852,81 +861,81 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCSR_FS	(1 << 0)	/* FIFO needs service */
 
 #define UDCBCN(x)	__REG2(0x40600200, (x)<<2)
-#define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
-#define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
-#define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
-#define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
-#define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
-#define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
-#define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
-#define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
-#define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
-#define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
-#define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
-#define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
-#define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
-#define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
-#define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
-#define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
-#define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
-#define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
-#define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
-#define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
-#define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
-#define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
-#define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
-#define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
+#define UDCBCR0         0x40600200 /* Byte Count Register - EP0 */
+#define UDCBCRA         0x40600204 /* Byte Count Register - EPA */
+#define UDCBCRB         0x40600208 /* Byte Count Register - EPB */
+#define UDCBCRC         0x4060020C /* Byte Count Register - EPC */
+#define UDCBCRD         0x40600210 /* Byte Count Register - EPD */
+#define UDCBCRE         0x40600214 /* Byte Count Register - EPE */
+#define UDCBCRF         0x40600218 /* Byte Count Register - EPF */
+#define UDCBCRG         0x4060021C /* Byte Count Register - EPG */
+#define UDCBCRH         0x40600220 /* Byte Count Register - EPH */
+#define UDCBCRI         0x40600224 /* Byte Count Register - EPI */
+#define UDCBCRJ         0x40600228 /* Byte Count Register - EPJ */
+#define UDCBCRK         0x4060022C /* Byte Count Register - EPK */
+#define UDCBCRL         0x40600230 /* Byte Count Register - EPL */
+#define UDCBCRM         0x40600234 /* Byte Count Register - EPM */
+#define UDCBCRN         0x40600238 /* Byte Count Register - EPN */
+#define UDCBCRP         0x4060023C /* Byte Count Register - EPP */
+#define UDCBCRQ         0x40600240 /* Byte Count Register - EPQ */
+#define UDCBCRR         0x40600244 /* Byte Count Register - EPR */
+#define UDCBCRS         0x40600248 /* Byte Count Register - EPS */
+#define UDCBCRT         0x4060024C /* Byte Count Register - EPT */
+#define UDCBCRU         0x40600250 /* Byte Count Register - EPU */
+#define UDCBCRV         0x40600254 /* Byte Count Register - EPV */
+#define UDCBCRW         0x40600258 /* Byte Count Register - EPW */
+#define UDCBCRX         0x4060025C /* Byte Count Register - EPX */
 
 #define UDCDN(x)	__REG2(0x40600300, (x)<<2)
-#define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
-#define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
-#define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
-#define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
-#define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
-#define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
-#define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
-#define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
-#define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
-#define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
-#define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
-#define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
-#define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
-#define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
-#define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
-#define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
-#define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
-#define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
-#define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
-#define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
-#define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
-#define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
-#define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
-#define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
+#define UDCDR0          0x40600300 /* Data Register - EP0 */
+#define UDCDRA          0x40600304 /* Data Register - EPA */
+#define UDCDRB          0x40600308 /* Data Register - EPB */
+#define UDCDRC          0x4060030C /* Data Register - EPC */
+#define UDCDRD          0x40600310 /* Data Register - EPD */
+#define UDCDRE          0x40600314 /* Data Register - EPE */
+#define UDCDRF          0x40600318 /* Data Register - EPF */
+#define UDCDRG          0x4060031C /* Data Register - EPG */
+#define UDCDRH          0x40600320 /* Data Register - EPH */
+#define UDCDRI          0x40600324 /* Data Register - EPI */
+#define UDCDRJ          0x40600328 /* Data Register - EPJ */
+#define UDCDRK          0x4060032C /* Data Register - EPK */
+#define UDCDRL          0x40600330 /* Data Register - EPL */
+#define UDCDRM          0x40600334 /* Data Register - EPM */
+#define UDCDRN          0x40600338 /* Data Register - EPN */
+#define UDCDRP          0x4060033C /* Data Register - EPP */
+#define UDCDRQ          0x40600340 /* Data Register - EPQ */
+#define UDCDRR          0x40600344 /* Data Register - EPR */
+#define UDCDRS          0x40600348 /* Data Register - EPS */
+#define UDCDRT          0x4060034C /* Data Register - EPT */
+#define UDCDRU          0x40600350 /* Data Register - EPU */
+#define UDCDRV          0x40600354 /* Data Register - EPV */
+#define UDCDRW          0x40600358 /* Data Register - EPW */
+#define UDCDRX          0x4060035C /* Data Register - EPX */
 
 #define UDCCN(x)	__REG2(0x40600400, (x)<<2)
-#define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
-#define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
-#define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
-#define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
-#define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
-#define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
-#define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
-#define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
-#define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
-#define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
-#define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
-#define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
-#define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
-#define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
-#define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
-#define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
-#define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
-#define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
-#define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
-#define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
-#define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
-#define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
-#define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
+#define UDCCRA          0x40600404 /* Configuration register EPA */
+#define UDCCRB          0x40600408 /* Configuration register EPB */
+#define UDCCRC          0x4060040C /* Configuration register EPC */
+#define UDCCRD          0x40600410 /* Configuration register EPD */
+#define UDCCRE          0x40600414 /* Configuration register EPE */
+#define UDCCRF          0x40600418 /* Configuration register EPF */
+#define UDCCRG          0x4060041C /* Configuration register EPG */
+#define UDCCRH          0x40600420 /* Configuration register EPH */
+#define UDCCRI          0x40600424 /* Configuration register EPI */
+#define UDCCRJ          0x40600428 /* Configuration register EPJ */
+#define UDCCRK          0x4060042C /* Configuration register EPK */
+#define UDCCRL          0x40600430 /* Configuration register EPL */
+#define UDCCRM          0x40600434 /* Configuration register EPM */
+#define UDCCRN          0x40600438 /* Configuration register EPN */
+#define UDCCRP          0x4060043C /* Configuration register EPP */
+#define UDCCRQ          0x40600440 /* Configuration register EPQ */
+#define UDCCRR          0x40600444 /* Configuration register EPR */
+#define UDCCRS          0x40600448 /* Configuration register EPS */
+#define UDCCRT          0x4060044C /* Configuration register EPT */
+#define UDCCRU          0x40600450 /* Configuration register EPU */
+#define UDCCRV          0x40600454 /* Configuration register EPV */
+#define UDCCRW          0x40600458 /* Configuration register EPW */
+#define UDCCRX          0x4060045C /* Configuration register EPX */
 
 #define UDCCONR_CN	(0x03 << 25)	/* Configuration Number */
 #define UDCCONR_CN_S	(25)
@@ -959,38 +968,39 @@ typedef void		(*ExcpHndlr) (void) ;
 
 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 
+/******************************************************************************/
 /*
  * USB Host Controller
  */
 #define OHCI_REGS_BASE	0x4C000000	/* required for ohci driver */
-#define UHCREV		__REG(0x4C000000)
-#define UHCHCON		__REG(0x4C000004)
-#define UHCCOMS		__REG(0x4C000008)
-#define UHCINTS		__REG(0x4C00000C)
-#define UHCINTE		__REG(0x4C000010)
-#define UHCINTD		__REG(0x4C000014)
-#define UHCHCCA		__REG(0x4C000018)
-#define UHCPCED		__REG(0x4C00001C)
-#define UHCCHED		__REG(0x4C000020)
-#define UHCCCED		__REG(0x4C000024)
-#define UHCBHED		__REG(0x4C000028)
-#define UHCBCED		__REG(0x4C00002C)
-#define UHCDHEAD	__REG(0x4C000030)
-#define UHCFMI		__REG(0x4C000034)
-#define UHCFMR		__REG(0x4C000038)
-#define UHCFMN		__REG(0x4C00003C)
-#define UHCPERS		__REG(0x4C000040)
-#define UHCLST		__REG(0x4C000044)
-#define UHCRHDA		__REG(0x4C000048)
-#define UHCRHDB		__REG(0x4C00004C)
-#define UHCRHS		__REG(0x4C000050)
-#define UHCRHPS1	__REG(0x4C000054)
-#define UHCRHPS2	__REG(0x4C000058)
-#define UHCRHPS3	__REG(0x4C00005C)
-#define UHCSTAT		__REG(0x4C000060)
-#define UHCHR		__REG(0x4C000064)
-#define UHCHIE		__REG(0x4C000068)
-#define UHCHIT		__REG(0x4C00006C)
+#define UHCREV		0x4C000000
+#define UHCHCON		0x4C000004
+#define UHCCOMS		0x4C000008
+#define UHCINTS		0x4C00000C
+#define UHCINTE		0x4C000010
+#define UHCINTD		0x4C000014
+#define UHCHCCA		0x4C000018
+#define UHCPCED		0x4C00001C
+#define UHCCHED		0x4C000020
+#define UHCCCED		0x4C000024
+#define UHCBHED		0x4C000028
+#define UHCBCED		0x4C00002C
+#define UHCDHEAD	0x4C000030
+#define UHCFMI		0x4C000034
+#define UHCFMR		0x4C000038
+#define UHCFMN		0x4C00003C
+#define UHCPERS		0x4C000040
+#define UHCLST		0x4C000044
+#define UHCRHDA		0x4C000048
+#define UHCRHDB		0x4C00004C
+#define UHCRHS		0x4C000050
+#define UHCRHPS1	0x4C000054
+#define UHCRHPS2	0x4C000058
+#define UHCRHPS3	0x4C00005C
+#define UHCSTAT		0x4C000060
+#define UHCHR		0x4C000064
+#define UHCHIE		0x4C000068
+#define UHCHIT		0x4C00006C
 
 #define UHCHR_FSBIR	(1<<0)
 #define UHCHR_FHR	(1<<1)
@@ -1011,9 +1021,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UHCHIE_HBAIE	(1<<8)
 #define UHCHIE_RWIE	(1<<7)
 
-#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
-#define UP2OCR		__REG(0x40600020)
-#endif
+#define UP2OCR		0x40600020
 
 #define UP2OCR_HXOE	(1<<17)
 #define UP2OCR_HXS	(1<<16)
@@ -1029,36 +1037,37 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UP2OCR_CPVPE	(1<<1)
 #define UP2OCR_CPVEN	(1<<0)
 
-#endif
+#endif	/* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
 
+/******************************************************************************/
 /*
  * Fast Infrared Communication Port
  */
-#define ICCR0		__REG(0x40800000)  /* ICP Control Register 0 */
-#define ICCR1		__REG(0x40800004)  /* ICP Control Register 1 */
-#define ICCR2		__REG(0x40800008)  /* ICP Control Register 2 */
-#define ICDR		__REG(0x4080000c)  /* ICP Data Register */
-#define ICSR0		__REG(0x40800014)  /* ICP Status Register 0 */
-#define ICSR1		__REG(0x40800018)  /* ICP Status Register 1 */
+#define ICCR0		0x40800000  /* ICP Control Register 0 */
+#define ICCR1		0x40800004  /* ICP Control Register 1 */
+#define ICCR2		0x40800008  /* ICP Control Register 2 */
+#define ICDR		0x4080000c  /* ICP Data Register */
+#define ICSR0		0x40800014  /* ICP Status Register 0 */
+#define ICSR1		0x40800018  /* ICP Status Register 1 */
 
 /*
  * Real Time Clock
  */
-#define RCNR		__REG(0x40900000)  /* RTC Count Register */
-#define RTAR		__REG(0x40900004)  /* RTC Alarm Register */
-#define RTSR		__REG(0x40900008)  /* RTC Status Register */
-#define RTTR		__REG(0x4090000C)  /* RTC Timer Trim Register */
-#define RDAR1		__REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
-#define RDAR2		__REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
-#define RYAR1		__REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
-#define RYAR2		__REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
-#define SWAR1		__REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
-#define SWAR2		__REG(0x40900030)  /* Stopwatch Alarm Register 2 */
-#define PIAR		__REG(0x40900038)  /* Periodic Interrupt Alarm Register */
-#define RDCR		__REG(0x40900010)  /* RTC Day Count Register. */
-#define RYCR		__REG(0x40900014)  /* RTC Year Count Register. */
-#define SWCR		__REG(0x40900028)  /* Stopwatch Count Register */
-#define RTCPICR		__REG(0x40900034)  /* Periodic Interrupt Counter Register */
+#define RCNR		0x40900000  /* RTC Count Register */
+#define RTAR		0x40900004  /* RTC Alarm Register */
+#define RTSR		0x40900008  /* RTC Status Register */
+#define RTTR		0x4090000C  /* RTC Timer Trim Register */
+#define RDAR1		0x40900018  /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2		0x40900020  /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1		0x4090001C  /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2		0x40900024  /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1		0x4090002C  /* Stopwatch Alarm Register 1 */
+#define SWAR2		0x40900030  /* Stopwatch Alarm Register 2 */
+#define PIAR		0x40900038  /* Periodic Interrupt Alarm Register */
+#define RDCR		0x40900010  /* RTC Day Count Register. */
+#define RYCR		0x40900014  /* RTC Year Count Register. */
+#define SWCR		0x40900028  /* Stopwatch Count Register */
+#define RTCPICR		0x40900034  /* Periodic Interrupt Counter Register */
 
 #define RTSR_PICE	(1 << 15)	/* Peridoc interrupt count enable */
 #define RTSR_PIALE	(1 << 14)	/* Peridoc interrupt Alarm enable */
@@ -1068,48 +1077,48 @@ typedef void		(*ExcpHndlr) (void) ;
 #define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
 #define RTSR_AL		(1 << 0)	/* RTC alarm detected */
 
+/******************************************************************************/
 /*
  * OS Timer & Match Registers
  */
-#define OSMR0		__REG(0x40A00000)  /* OS Timer Match Register 0 */
-#define OSMR1		__REG(0x40A00004)  /* OS Timer Match Register 1 */
-#define OSMR2		__REG(0x40A00008)  /* OS Timer Match Register 2 */
-#define OSMR3		__REG(0x40A0000C)  /* OS Timer Match Register 3 */
-#define OSCR		__REG(0x40A00010)  /* OS Timer Counter Register */
-#define OSSR		__REG(0x40A00014)  /* OS Timer Status Register */
-#define OWER		__REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
-#define OIER		__REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
+#define OSMR0		0x40A00000  /* OS Timer Match Register 0 */
+#define OSMR1		0x40A00004  /* OS Timer Match Register 1 */
+#define OSMR2		0x40A00008  /* OS Timer Match Register 2 */
+#define OSMR3		0x40A0000C  /* OS Timer Match Register 3 */
+#define OSCR		0x40A00010  /* OS Timer Counter Register */
+#define OSSR		0x40A00014  /* OS Timer Status Register */
+#define OWER		0x40A00018  /* OS Timer Watchdog Enable Register */
+#define OIER		0x40A0001C  /* OS Timer Interrupt Enable Register */
 
-#ifdef CONFIG_CPU_MONAHANS
-#define OSCR4		__REG(0x40A00040)  /* OS Timer Counter Register 4 */
-#define OSCR5		__REG(0x40A00044)  /* OS Timer Counter Register 5 */
-#define OSCR6		__REG(0x40A00048)  /* OS Timer Counter Register 6 */
-#define OSCR7		__REG(0x40A0004C)  /* OS Timer Counter Register 7 */
-#define OSCR8		__REG(0x40A00050)  /* OS Timer Counter Register 8 */
-#define OSCR9		__REG(0x40A00054)  /* OS Timer Counter Register 9 */
-#define OSCR10		__REG(0x40A00058)  /* OS Timer Counter Register 10 */
-#define OSCR11		__REG(0x40A0005C)  /* OS Timer Counter Register 11 */
-
-#define OSMR4		__REG(0x40A00080)  /* OS Timer Match Register 4 */
-#define OSMR5		__REG(0x40A00084)  /* OS Timer Match Register 5 */
-#define OSMR6		__REG(0x40A00088)  /* OS Timer Match Register 6 */
-#define OSMR7		__REG(0x40A0008C)  /* OS Timer Match Register 7 */
-#define OSMR8		__REG(0x40A00090)  /* OS Timer Match Register 8 */
-#define OSMR9		__REG(0x40A00094)  /* OS Timer Match Register 9 */
-#define OSMR10		__REG(0x40A00098)  /* OS Timer Match Register 10 */
-#define OSMR11		__REG(0x40A0009C)  /* OS Timer Match Register 11 */
-
-#define OMCR4		__REG(0x40A000C0)  /* OS Match Control Register 4 */
-#define OMCR5		__REG(0x40A000C4)  /* OS Match Control Register 5 */
-#define OMCR6		__REG(0x40A000C8)  /* OS Match Control Register 6 */
-#define OMCR7		__REG(0x40A000CC)  /* OS Match Control Register 7 */
-#define OMCR8		__REG(0x40A000D0)  /* OS Match Control Register 8 */
-#define OMCR9		__REG(0x40A000D4)  /* OS Match Control Register 9 */
-#define OMCR10		__REG(0x40A000D8)  /* OS Match Control Register 10 */
-#define OMCR11		__REG(0x40A000DC)  /* OS Match Control Register 11 */
-
-#define OSCR_CLK_FREQ	 3250		   /* kHz = 3.25 MHz */
-#endif /* CONFIG_CPU_MONAHANS */
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define OSCR4		0x40A00040  /* OS Timer Counter Register 4 */
+#define OSCR5		0x40A00044  /* OS Timer Counter Register 5 */
+#define OSCR6		0x40A00048  /* OS Timer Counter Register 6 */
+#define OSCR7		0x40A0004C  /* OS Timer Counter Register 7 */
+#define OSCR8		0x40A00050  /* OS Timer Counter Register 8 */
+#define OSCR9		0x40A00054  /* OS Timer Counter Register 9 */
+#define OSCR10		0x40A00058  /* OS Timer Counter Register 10 */
+#define OSCR11		0x40A0005C  /* OS Timer Counter Register 11 */
+
+#define OSMR4		0x40A00080  /* OS Timer Match Register 4 */
+#define OSMR5		0x40A00084  /* OS Timer Match Register 5 */
+#define OSMR6		0x40A00088  /* OS Timer Match Register 6 */
+#define OSMR7		0x40A0008C  /* OS Timer Match Register 7 */
+#define OSMR8		0x40A00090  /* OS Timer Match Register 8 */
+#define OSMR9		0x40A00094  /* OS Timer Match Register 9 */
+#define OSMR10		0x40A00098  /* OS Timer Match Register 10 */
+#define OSMR11		0x40A0009C  /* OS Timer Match Register 11 */
+
+#define OMCR4		0x40A000C0  /* OS Match Control Register 4 */
+#define OMCR5		0x40A000C4  /* OS Match Control Register 5 */
+#define OMCR6		0x40A000C8  /* OS Match Control Register 6 */
+#define OMCR7		0x40A000CC  /* OS Match Control Register 7 */
+#define OMCR8		0x40A000D0  /* OS Match Control Register 8 */
+#define OMCR9		0x40A000D4  /* OS Match Control Register 9 */
+#define OMCR10		0x40A000D8  /* OS Match Control Register 10 */
+#define OMCR11		0x40A000DC  /* OS Match Control Register 11 */
+
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
 
 #define OSSR_M4		(1 << 4)	/* Match status channel 4 */
 #define OSSR_M3		(1 << 3)	/* Match status channel 3 */
@@ -1125,321 +1134,696 @@ typedef void		(*ExcpHndlr) (void) ;
 #define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
 #define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
 
+#define	OSCR_CLK_FREQ	3250
+
+/******************************************************************************/
 /*
- * Pulse Width Modulator
+ * Core Clock
  */
-#define PWM_CTRL0	__REG(0x40B00000)  /* PWM 0 Control Register */
-#define PWM_PWDUTY0	__REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
-#define PWM_PERVAL0	__REG(0x40B00008)  /* PWM 0 Period Control Register */
 
-#define PWM_CTRL1	__REG(0x40C00000)  /* PWM 1 Control Register */
-#define PWM_PWDUTY1	__REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
-#define PWM_PERVAL1	__REG(0x40C00008)  /* PWM 1 Period Control Register */
+#if defined(CONFIG_CPU_MONAHANS)
+#define ACCR		0x41340000  /* Application Subsystem Clock Configuration Register */
+#define ACSR		0x41340004  /* Application Subsystem Clock Status Register */
+#define AICSR		0x41340008  /* Application Subsystem Interrupt Control/Status Register */
+#define CKENA		0x4134000C  /* A Clock Enable Register */
+#define CKENB		0x41340010  /* B Clock Enable Register */
+#define AC97_DIV	0x41340014  /* AC97 clock divisor value register */
+
+#define ACCR_SMC_MASK	0x03800000	/* Static Memory Controller Frequency Select */
+#define ACCR_SRAM_MASK	0x000c0000	/* SRAM Controller Frequency Select */
+#define ACCR_FC_MASK	0x00030000	/* Frequency Change Frequency Select */
+#define ACCR_HSIO_MASK	0x0000c000	/* High Speed IO Frequency Select */
+#define ACCR_DDR_MASK	0x00003000	/* DDR Memory Controller Frequency Select */
+#define ACCR_XN_MASK	0x00000700	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define ACCR_XL_MASK	0x0000001f	/* Crystal Frequency to Memory Frequency Multiplier */
+#define ACCR_XPDIS	(1 << 31)
+#define ACCR_SPDIS	(1 << 30)
+#define ACCR_13MEND1	(1 << 27)
+#define ACCR_D0CS	(1 << 26)
+#define ACCR_13MEND2	(1 << 21)
+#define ACCR_PCCE	(1 << 11)
+
+#define CKENA_30_MSL0	(1 << 30)	/* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4	(1 << 29)	/* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3	(1 << 28)	/* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2	(1 << 27)	/* SSP1 Unit Clock Enable */
+#define CKENA_26_SSP1	(1 << 26)	/* SSP0 Unit Clock Enable */
+#define CKENA_25_TSI	(1 << 25)	/* TSI Clock Enable */
+#define CKENA_24_AC97	(1 << 24)	/* AC97 Unit Clock Enable */
+#define CKENA_23_STUART	(1 << 23)	/* STUART Unit Clock Enable */
+#define CKENA_22_FFUART	(1 << 22)	/* FFUART Unit Clock Enable */
+#define CKENA_21_BTUART	(1 << 21)	/* BTUART Unit Clock Enable */
+#define CKENA_20_UDC	(1 << 20)	/* UDC Clock Enable */
+#define CKENA_19_TPM	(1 << 19)	/* TPM Unit Clock Enable */
+#define CKENA_18_USIM1	(1 << 18)	/* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0	(1 << 17)	/* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR	(1 << 15)	/* Consumer IR Clock Enable */
+#define CKENA_14_KEY	(1 << 14)	/* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1	(1 << 13)	/* MMC1 Clock Enable */
+#define CKENA_12_MMC0	(1 << 12)	/* MMC0 Clock Enable */
+#define CKENA_11_FLASH	(1 << 11)	/* Boot ROM Clock Enable */
+#define CKENA_10_SRAM	(1 << 10)	/* SRAM Controller Clock Enable */
+#define CKENA_9_SMC	(1 << 9)	/* Static Memory Controller */
+#define CKENA_8_DMC	(1 << 8)	/* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7)	/* 2D Graphics Clock Enable */
+#define CKENA_6_USBCLI	(1 << 6)	/* USB Client Unit Clock Enable */
+#define CKENA_4_NAND	(1 << 4)	/* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA	(1 << 3)	/* Camera Interface Clock Enable */
+#define CKENA_2_USBHOST	(1 << 2)	/* USB Host Unit Clock Enable */
+#define CKENA_1_LCD	(1 << 1)	/* LCD Unit Clock Enable */
+
+#define CKENB_9_SYSBUS2	(1 << 9)	/* System bus 2 */
+#define CKENB_8_1WIRE	(1 << 8)	/* One Wire Interface Unit Clock Enable */
+#define CKENB_7_GPIO	(1 << 7)	/* GPIO Clock Enable */
+#define CKENB_6_IRQ	(1 << 6)	/* Interrupt Controller Clock Enable */
+#define CKENB_4_I2C	(1 << 4)	/* I2C Unit Clock Enable */
+#define CKENB_1_PWM1	(1 << 1)	/* PWM2 & PWM3 Clock Enable */
+#define CKENB_0_PWM0	(1 << 0)	/* PWM0 & PWM1 Clock Enable */
+
+#else /* if defined CONFIG_CPU_MONAHANS */
+
+#define CCCR		0x41300000  /* Core Clock Configuration Register */
+#define CKEN		0x41300004  /* Clock Enable Register */
+#define OSCC		0x41300008  /* Oscillator Configuration Register */
+#define CCSR		0x4130000C /* Core Clock Status Register */
+
+#define CKEN23_SSP1	(1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22) /* Memory Controler */
+#define CKEN21_MSHC	(1 << 21) /* Memery Stick Host Controller */
+#define CKEN20_IM	(1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17) /* MSL Interface Unit Clock Enable */
+#define CKEN15_PWR_I2C	(1 << 15) /* PWR_I2C Unit Clock Enable */
+#define CKEN9_OST	(1 << 9)  /* OS Timer Unit Clock Enable */
+#define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
+
+#define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#if !defined(CONFIG_PXA27X)
+#define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
+#endif
+#define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Interface Clock Enable */
+#define CKEN23_SSP1	(1 << 23)	/* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22)	/* Memory Controller Clock Enable */
+#define CKEN21_MEMSTK	(1 << 21)	/* Memory Stick Host Controller */
+#define CKEN20_IM	(1 << 20)	/* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19)	/* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18)	/* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17)	/* MSL Unit Clock Enable */
+#define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */
+#define CKEN15_PWRI2C	(1 << 15)	/* PWR I2C Unit Clock Enable */
+#define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */
+#define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
+#define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
+#define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
+#if defined(CONFIG_PXA27X)
+#define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
+#endif
+#define CKEN8_I2S	(1 << 8)	/* I2S Unit Clock Enable */
+#define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
+#define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
+#define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */
+#define CKEN3_SSP	(1 << 3)	/* SSP Unit Clock Enable */
+#define CKEN2_AC97	(1 << 2)	/* AC97 Unit Clock Enable */
+#define CKEN1_PWM1	(1 << 1)	/* PWM1 Clock Enable */
+#define CKEN0_PWM0	(1 << 0)	/* PWM0 Clock Enable */
+
+#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
+
+#if !defined(CONFIG_PXA27X)
+#define	 CCCR_L09      (0x1F)
+#define	 CCCR_L27      (0x1)
+#define	 CCCR_L32      (0x2)
+#define	 CCCR_L36      (0x3)
+#define	 CCCR_L40      (0x4)
+#define	 CCCR_L45      (0x5)
+
+#define	 CCCR_M1       (0x1 << 5)
+#define	 CCCR_M2       (0x2 << 5)
+#define	 CCCR_M4       (0x3 << 5)
 
-#define PWM_CTRL2	__REG(0x40B00010)  /* PWM 2 Control Register */
-#define PWM_PWDUTY2	__REG(0x40B00014)  /* PWM 2 Duty Cycle Register */
-#define PWM_PERVAL2	__REG(0x40B00018)  /* PWM 2 Period Control Register */
+#define	 CCCR_N10      (0x2 << 7)
+#define	 CCCR_N15      (0x3 << 7)
+#define	 CCCR_N20      (0x4 << 7)
+#define	 CCCR_N25      (0x5 << 7)
+#define	 CCCR_N30      (0x6 << 7)
+#endif
 
-#define PWM_CTRL3	__REG(0x40C00010)  /* PWM 3 Control Register */
-#define PWM_PWDUTY3	__REG(0x40C00014)  /* PWM 3 Duty Cycle Register */
-#define PWM_PERVAL3	__REG(0x40C00018)  /* PWM 3 Period Control Register */
+#endif /* CONFIG_CPU_MONAHANS */
 
+/******************************************************************************/
 /*
- * Interrupt Controller
+ * Pulse Width Modulator
  */
-#define ICIP		__REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
-#define ICMR		__REG(0x40D00004)  /* Interrupt Controller Mask Register */
-#define ICLR		__REG(0x40D00008)  /* Interrupt Controller Level Register */
-#define ICFP		__REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
-#define ICPR		__REG(0x40D00010)  /* Interrupt Controller Pending Register */
-#define ICCR		__REG(0x40D00014)  /* Interrupt Controller Control Register */
+#define PWM_CTRL0	0x40B00000  /* PWM 0 Control Register */
+#define PWM_PWDUTY0	0x40B00004  /* PWM 0 Duty Cycle Register */
+#define PWM_PERVAL0	0x40B00008  /* PWM 0 Period Control Register */
 
-#ifdef CONFIG_CPU_MONAHANS
-#define ICHP		__REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
-/* Missing: 32 Interrupt priority registers
- * These are the same as beneath for PXA27x: maybe can be merged if
- * GPIO Stuff is same too.
+#define PWM_CTRL1	0x40C00000  /* PWM 1 Control Register */
+#define PWM_PWDUTY1	0x40C00004  /* PWM 1 Duty Cycle Register */
+#define PWM_PERVAL1	0x40C00008  /* PWM 1 Period Control Register */
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define PWM_CTRL2	0x40B00010  /* PWM 2 Control Register */
+#define PWM_PWDUTY2	0x40B00014  /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2	0x40B00018  /* PWM 2 Period Control Register */
+
+#define PWM_CTRL3	0x40C00010  /* PWM 3 Control Register */
+#define PWM_PWDUTY3	0x40C00014  /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3	0x40C00018  /* PWM 3 Period Control Register */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+
+/*
+ * Interrupt Controller
  */
-#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
-#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
-#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
-/* Missing: 2 Interrupt priority registers */
-#endif /* CONFIG_CPU_MONAHANS */
+#define ICIP		0x40D00000  /* Interrupt Controller IRQ Pending Register */
+#define ICMR		0x40D00004  /* Interrupt Controller Mask Register */
+#define ICLR		0x40D00008  /* Interrupt Controller Level Register */
+#define ICFP		0x40D0000C  /* Interrupt Controller FIQ Pending Register */
+#define ICPR		0x40D00010  /* Interrupt Controller Pending Register */
+#define ICCR		0x40D00014  /* Interrupt Controller Control Register */
 
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define ICHP		0x40D00018  /* Interrupt Controller Highest Priority Register */
+#define ICIP2		0x40D0009C  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2		0x40D000A0  /* Interrupt Controller Mask Register 2 */
+#define ICLR2		0x40D000A4  /* Interrupt Controller Level Register 2 */
+#define ICFP2		0x40D000A8  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2		0x40D000AC  /* Interrupt Controller Pending Register 2 */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+
+/******************************************************************************/
 /*
  * General Purpose I/O
  */
-#define GPLR0		__REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
-#define GPLR1		__REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
-#define GPLR2		__REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
+#define GPLR0		0x40E00000  /* GPIO Pin-Level Register GPIO<31:0> */
+#define GPLR1		0x40E00004  /* GPIO Pin-Level Register GPIO<63:32> */
+#define GPLR2		0x40E00008  /* GPIO Pin-Level Register GPIO<80:64> */
 
-#define GPDR0		__REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
-#define GPDR1		__REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
-#define GPDR2		__REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */
+#define GPDR0		0x40E0000C  /* GPIO Pin Direction Register GPIO<31:0> */
+#define GPDR1		0x40E00010  /* GPIO Pin Direction Register GPIO<63:32> */
+#define GPDR2		0x40E00014  /* GPIO Pin Direction Register GPIO<80:64> */
 
-#define GPSR0		__REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
-#define GPSR1		__REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
-#define GPSR2		__REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */
+#define GPSR0		0x40E00018  /* GPIO Pin Output Set Register GPIO<31:0> */
+#define GPSR1		0x40E0001C  /* GPIO Pin Output Set Register GPIO<63:32> */
+#define GPSR2		0x40E00020  /* GPIO Pin Output Set Register GPIO<80:64> */
 
-#define GPCR0		__REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
-#define GPCR1		__REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
-#define GPCR2		__REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */
+#define GPCR0		0x40E00024  /* GPIO Pin Output Clear Register GPIO<31:0> */
+#define GPCR1		0x40E00028  /* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2		0x40E0002C  /* GPIO Pin Output Clear Register GPIO <80:64> */
 
-#define GRER0		__REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
-#define GRER1		__REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
-#define GRER2		__REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
+#define GRER0		0x40E00030  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
+#define GRER1		0x40E00034  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
+#define GRER2		0x40E00038  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
 
-#define GFER0		__REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
-#define GFER1		__REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
-#define GFER2		__REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
+#define GFER0		0x40E0003C  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GFER1		0x40E00040  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
+#define GFER2		0x40E00044  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
 
-#define GEDR0		__REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
-#define GEDR1		__REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
-#define GEDR2		__REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
+#define GEDR0		0x40E00048  /* GPIO Edge Detect Status Register GPIO<31:0> */
+#define GEDR1		0x40E0004C  /* GPIO Edge Detect Status Register GPIO<63:32> */
+#define GEDR2		0x40E00050  /* GPIO Edge Detect Status Register GPIO<80:64> */
+
+#define GAFR0_L		0x40E00054  /* GPIO Alternate Function Select Register GPIO<15:0> */
+#define GAFR0_U		0x40E00058  /* GPIO Alternate Function Select Register GPIO<31:16> */
+#define GAFR1_L		0x40E0005C  /* GPIO Alternate Function Select Register GPIO<47:32> */
+#define GAFR1_U		0x40E00060  /* GPIO Alternate Function Select Register GPIO<63:48> */
+#define GAFR2_L		0x40E00064  /* GPIO Alternate Function Select Register GPIO<79:64> */
+#define GAFR2_U		0x40E00068  /* GPIO Alternate Function Select Register GPIO 80 */
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR3		0x40E00100  /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3		0x40E0010C  /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3		0x40E00118  /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3		0x40E00124  /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3		0x40E00130  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3		0x40E0013C  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3		0x40E00148  /* GPIO Edge Detect Status Register GPIO<127:96> */
+#define GAFR3_L		0x40E0006C  /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U		0x40E00070  /* GPIO Alternate Function Select Register GPIO<127:112> */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
 
 #ifdef CONFIG_CPU_MONAHANS
-#define GPLR3		__REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
-#define GPDR3		__REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
-#define GPSR3		__REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
-#define GPCR3		__REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
-#define GRER3		__REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
-#define GFER3		__REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
-#define GEDR3		__REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
-
-#define GSDR0		__REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
-#define GSDR1		__REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
-#define GSDR2		__REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
-#define GSDR3		__REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */
-
-#define GCDR0		__REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
-#define GCDR1		__REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
-#define GCDR2		__REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
-#define GCDR3		__REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
-
-#define GSRER0		__REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
-#define GSRER1		__REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
-#define GSRER2		__REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
-#define GSRER3		__REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
-
-#define GCRER0		__REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
-#define GCRER1		__REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
-#define GCRER2		__REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
-#define GCRER3		__REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
-
-#define GSFER0		__REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
-#define GSFER1		__REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
-#define GSFER2		__REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
-#define GSFER3		__REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
-
-#define GCFER0		__REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
-#define GCFER1		__REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
-#define GCFER2		__REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
-#define GCFER3		__REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
-
-#define GSDR(x)		__REG2(0x40E00400, ((x) & 0x60) >> 3)
-#define GCDR(x)		__REG2(0x40E00420, ((x) & 0x60) >> 3)
-
-/* Multi-funktion Pin Registers, uncomplete, only:
- *    - GPIO
- *    - Data Flash DF_* pins defined.
+#define GSDR0		0x40E00400 /* Bit-wise Set of GPDR[31:0] */
+#define GSDR1		0x40E00404 /* Bit-wise Set of GPDR[63:32] */
+#define GSDR2		0x40E00408 /* Bit-wise Set of GPDR[95:64] */
+#define GSDR3		0x40E0040C /* Bit-wise Set of GPDR[127:96] */
+
+#define GCDR0		0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
+#define GCDR1		0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
+#define GCDR2		0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
+#define GCDR3		0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
+
+#define GSRER0		0x40E00440 /* Set Rising Edge Det. Enable [31:0] */
+#define GSRER1		0x40E00444 /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER2		0x40E00448 /* Set Rising Edge Det. Enable [95:64] */
+#define GSRER3		0x40E0044C /* Set Rising Edge Det. Enable [127:96] */
+
+#define GCRER0		0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */
+#define GCRER1		0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER2		0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */
+#define GCRER3		0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */
+
+#define GSFER0		0x40E00480 /* Set Falling Edge Det. Enable [31:0] */
+#define GSFER1		0x40E00484 /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER2		0x40E00488 /* Set Falling Edge Det. Enable [95:64] */
+#define GSFER3		0x40E0048C /* Set Falling Edge Det. Enable[127:96] */
+
+#define GCFER0		0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */
+#define GCFER1		0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER2		0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */
+#define GCFER3		0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */
+
+#define GSDR(x)		(0x40E00400 | ((x) & 0x60) >> 3)
+#define GCDR(x)		(0x40E00420 | ((x) & 0x60) >> 3)
+#endif
+
+#define _GPLR(x)	(0x40E00000 + (((x) & 0x60) >> 3))
+#define _GPDR(x)	(0x40E0000C + (((x) & 0x60) >> 3))
+#define _GPSR(x)	(0x40E00018 + (((x) & 0x60) >> 3))
+#define _GPCR(x)	(0x40E00024 + (((x) & 0x60) >> 3))
+#define _GRER(x)	(0x40E00030 + (((x) & 0x60) >> 3))
+#define _GFER(x)	(0x40E0003C + (((x) & 0x60) >> 3))
+#define _GEDR(x)	(0x40E00048 + (((x) & 0x60) >> 3))
+#define _GAFR(x)	(0x40E00054 + (((x) & 0x70) >> 2))
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR(x)		(((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
+#define GPDR(x)		(((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
+#define GPSR(x)		(((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
+#define GPCR(x)		(((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3))
+#define GRER(x)		(((((x) & 0x7f) < 96) ? _GRER(x) : GRER3))
+#define GFER(x)		(((((x) & 0x7f) < 96) ? _GFER(x) : GFER3))
+#define GEDR(x)		(((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3))
+#define GAFR(x)		(((((x) & 0x7f) < 96) ? _GAFR(x) : \
+			((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)))
+#else
+#define GPLR(x)		_GPLR(x)
+#define GPDR(x)		_GPDR(x)
+#define GPSR(x)		_GPSR(x)
+#define GPCR(x)		_GPCR(x)
+#define GRER(x)		_GRER(x)
+#define GFER(x)		_GFER(x)
+#define GEDR(x)		_GEDR(x)
+#define GAFR(x)		_GAFR(x)
+#endif
+
+#define GPIO_bit(x)	(1 << ((x) & 0x1f))
+
+/******************************************************************************/
+/*
+ * Multi-function Pin Registers:
  */
-#define GPIO0		__REG(0x40e10124)
-#define GPIO1		__REG(0x40e10128)
-#define GPIO2		__REG(0x40e1012c)
-#define GPIO3		__REG(0x40e10130)
-#define GPIO4		__REG(0x40e10134)
-#define nXCVREN		__REG(0x40e10138)
-
-#define DF_CLE_NOE	__REG(0x40e10204)
-#define DF_ALE_WE1	__REG(0x40e10208)
-
-#define DF_SCLK_E	__REG(0x40e10210)
-#define nBE0		__REG(0x40e10214)
-#define nBE1		__REG(0x40e10218)
-#define DF_ALE_WE2	__REG(0x40e1021c)
-#define DF_INT_RnB	__REG(0x40e10220)
-#define DF_nCS0		__REG(0x40e10224)
-#define DF_nCS1		__REG(0x40e10228)
-#define DF_nWE		__REG(0x40e1022c)
-#define DF_nRE		__REG(0x40e10230)
-#define nLUA		__REG(0x40e10234)
-#define nLLA		__REG(0x40e10238)
-#define DF_ADDR0	__REG(0x40e1023c)
-#define DF_ADDR1	__REG(0x40e10240)
-#define DF_ADDR2	__REG(0x40e10244)
-#define DF_ADDR3	__REG(0x40e10248)
-#define DF_IO0		__REG(0x40e1024c)
-#define DF_IO8		__REG(0x40e10250)
-#define DF_IO1		__REG(0x40e10254)
-#define DF_IO9		__REG(0x40e10258)
-#define DF_IO2		__REG(0x40e1025c)
-#define DF_IO10		__REG(0x40e10260)
-#define DF_IO3		__REG(0x40e10264)
-#define DF_IO11		__REG(0x40e10268)
-#define DF_IO4		__REG(0x40e1026c)
-#define DF_IO12		__REG(0x40e10270)
-#define DF_IO5		__REG(0x40e10274)
-#define DF_IO13		__REG(0x40e10278)
-#define DF_IO6		__REG(0x40e1027c)
-#define DF_IO14		__REG(0x40e10280)
-#define DF_IO7		__REG(0x40e10284)
-#define DF_IO15		__REG(0x40e10288)
-
-#define GPIO5		__REG(0x40e1028c)
-#define GPIO6		__REG(0x40e10290)
-#define GPIO7		__REG(0x40e10294)
-#define GPIO8		__REG(0x40e10298)
-#define GPIO9		__REG(0x40e1029c)
-
-#define GPIO11		__REG(0x40e102a0)
-#define GPIO12		__REG(0x40e102a4)
-#define GPIO13		__REG(0x40e102a8)
-#define GPIO14		__REG(0x40e102ac)
-#define GPIO15		__REG(0x40e102b0)
-#define GPIO16		__REG(0x40e102b4)
-#define GPIO17		__REG(0x40e102b8)
-#define GPIO18		__REG(0x40e102bc)
-#define GPIO19		__REG(0x40e102c0)
-#define GPIO20		__REG(0x40e102c4)
-#define GPIO21		__REG(0x40e102c8)
-#define GPIO22		__REG(0x40e102cc)
-#define GPIO23		__REG(0x40e102d0)
-#define GPIO24		__REG(0x40e102d4)
-#define GPIO25		__REG(0x40e102d8)
-#define GPIO26		__REG(0x40e102dc)
-
-#define GPIO27		__REG(0x40e10400)
-#define GPIO28		__REG(0x40e10404)
-#define GPIO29		__REG(0x40e10408)
-#define GPIO30		__REG(0x40e1040c)
-#define GPIO31		__REG(0x40e10410)
-#define GPIO32		__REG(0x40e10414)
-#define GPIO33		__REG(0x40e10418)
-#define GPIO34		__REG(0x40e1041c)
-#define GPIO35		__REG(0x40e10420)
-#define GPIO36		__REG(0x40e10424)
-#define GPIO37		__REG(0x40e10428)
-#define GPIO38		__REG(0x40e1042c)
-#define GPIO39		__REG(0x40e10430)
-#define GPIO40		__REG(0x40e10434)
-#define GPIO41		__REG(0x40e10438)
-#define GPIO42		__REG(0x40e1043c)
-#define GPIO43		__REG(0x40e10440)
-#define GPIO44		__REG(0x40e10444)
-#define GPIO45		__REG(0x40e10448)
-#define GPIO46		__REG(0x40e1044c)
-#define GPIO47		__REG(0x40e10450)
-#define GPIO48		__REG(0x40e10454)
-
-#define GPIO10		__REG(0x40e10458)
-
-#define GPIO49		__REG(0x40e1045c)
-#define GPIO50		__REG(0x40e10460)
-#define GPIO51		__REG(0x40e10464)
-#define GPIO52		__REG(0x40e10468)
-#define GPIO53		__REG(0x40e1046c)
-#define GPIO54		__REG(0x40e10470)
-#define GPIO55		__REG(0x40e10474)
-#define GPIO56		__REG(0x40e10478)
-#define GPIO57		__REG(0x40e1047c)
-#define GPIO58		__REG(0x40e10480)
-#define GPIO59		__REG(0x40e10484)
-#define GPIO60		__REG(0x40e10488)
-#define GPIO61		__REG(0x40e1048c)
-#define GPIO62		__REG(0x40e10490)
-
-#define GPIO6_2		__REG(0x40e10494)
-#define GPIO7_2		__REG(0x40e10498)
-#define GPIO8_2		__REG(0x40e1049c)
-#define GPIO9_2		__REG(0x40e104a0)
-#define GPIO10_2	__REG(0x40e104a4)
-#define GPIO11_2	__REG(0x40e104a8)
-#define GPIO12_2	__REG(0x40e104ac)
-#define GPIO13_2	__REG(0x40e104b0)
-
-#define GPIO63		__REG(0x40e104b4)
-#define GPIO64		__REG(0x40e104b8)
-#define GPIO65		__REG(0x40e104bc)
-#define GPIO66		__REG(0x40e104c0)
-#define GPIO67		__REG(0x40e104c4)
-#define GPIO68		__REG(0x40e104c8)
-#define GPIO69		__REG(0x40e104cc)
-#define GPIO70		__REG(0x40e104d0)
-#define GPIO71		__REG(0x40e104d4)
-#define GPIO72		__REG(0x40e104d8)
-#define GPIO73		__REG(0x40e104dc)
-
-#define GPIO14_2	__REG(0x40e104e0)
-#define GPIO15_2	__REG(0x40e104e4)
-#define GPIO16_2	__REG(0x40e104e8)
-#define GPIO17_2	__REG(0x40e104ec)
-
-#define GPIO74		__REG(0x40e104f0)
-#define GPIO75		__REG(0x40e104f4)
-#define GPIO76		__REG(0x40e104f8)
-#define GPIO77		__REG(0x40e104fc)
-#define GPIO78		__REG(0x40e10500)
-#define GPIO79		__REG(0x40e10504)
-#define GPIO80		__REG(0x40e10508)
-#define GPIO81		__REG(0x40e1050c)
-#define GPIO82		__REG(0x40e10510)
-#define GPIO83		__REG(0x40e10514)
-#define GPIO84		__REG(0x40e10518)
-#define GPIO85		__REG(0x40e1051c)
-#define GPIO86		__REG(0x40e10520)
-#define GPIO87		__REG(0x40e10524)
-#define GPIO88		__REG(0x40e10528)
-#define GPIO89		__REG(0x40e1052c)
-#define GPIO90		__REG(0x40e10530)
-#define GPIO91		__REG(0x40e10534)
-#define GPIO92		__REG(0x40e10538)
-#define GPIO93		__REG(0x40e1053c)
-#define GPIO94		__REG(0x40e10540)
-#define GPIO95		__REG(0x40e10544)
-#define GPIO96		__REG(0x40e10548)
-#define GPIO97		__REG(0x40e1054c)
-#define GPIO98		__REG(0x40e10550)
-
-#define GPIO99		__REG(0x40e10600)
-#define GPIO100		__REG(0x40e10604)
-#define GPIO101		__REG(0x40e10608)
-#define GPIO102		__REG(0x40e1060c)
-#define GPIO103		__REG(0x40e10610)
-#define GPIO104		__REG(0x40e10614)
-#define GPIO105		__REG(0x40e10618)
-#define GPIO106		__REG(0x40e1061c)
-#define GPIO107		__REG(0x40e10620)
-#define GPIO108		__REG(0x40e10624)
-#define GPIO109		__REG(0x40e10628)
-#define GPIO110		__REG(0x40e1062c)
-#define GPIO111		__REG(0x40e10630)
-#define GPIO112		__REG(0x40e10634)
-
-#define GPIO113		__REG(0x40e10638)
-#define GPIO114		__REG(0x40e1063c)
-#define GPIO115		__REG(0x40e10640)
-#define GPIO116		__REG(0x40e10644)
-#define GPIO117		__REG(0x40e10648)
-#define GPIO118		__REG(0x40e1064c)
-#define GPIO119		__REG(0x40e10650)
-#define GPIO120		__REG(0x40e10654)
-#define GPIO121		__REG(0x40e10658)
-#define GPIO122		__REG(0x40e1065c)
-#define GPIO123		__REG(0x40e10660)
-#define GPIO124		__REG(0x40e10664)
-#define GPIO125		__REG(0x40e10668)
-#define GPIO126		__REG(0x40e1066c)
-#define GPIO127		__REG(0x40e10670)
-
-#define GPIO0_2		__REG(0x40e10674)
-#define GPIO1_2		__REG(0x40e10678)
-#define GPIO2_2		__REG(0x40e1067c)
-#define GPIO3_2		__REG(0x40e10680)
-#define GPIO4_2		__REG(0x40e10684)
-#define GPIO5_2		__REG(0x40e10688)
+/* PXA320 */
+#if defined(CONFIG_CPU_PXA320)
+#define	DF_IO0		0x40e1024c
+#define	DF_IO1		0x40e10254
+#define	DF_IO2		0x40e1025c
+#define	DF_IO3		0x40e10264
+#define	DF_IO4		0x40e1026c
+#define	DF_IO5		0x40e10274
+#define	DF_IO6		0x40e1027c
+#define	DF_IO7		0x40e10284
+#define	DF_IO8		0x40e10250
+#define	DF_IO9		0x40e10258
+#define	DF_IO10		0x40e10260
+#define	DF_IO11		0x40e10268
+#define	DF_IO12		0x40e10270
+#define	DF_IO13		0x40e10278
+#define	DF_IO14		0x40e10280
+#define	DF_IO15		0x40e10288
+#define	DF_CLE_nOE	0x40e10204
+#define	DF_ALE_nWE1	0x40e10208
+#define	DF_ALE_nWE2	0x40e1021c
+#define	DF_SCLK_E	0x40e10210
+#define	DF_nCS0		0x40e10224
+#define	DF_nCS1		0x40e10228
+#define	nBE0		0x40e10214
+#define	nBE1		0x40e10218
+#define	nLUA		0x40e10234
+#define	nLLA		0x40e10238
+#define	DF_ADDR0	0x40e1023c
+#define	DF_ADDR1	0x40e10240
+#define	DF_ADDR2	0x40e10244
+#define	DF_ADDR3	0x40e10248
+#define	DF_INT_RnB	0x40e10220
+#define	DF_nCS0		0x40e10224
+#define	DF_nCS1		0x40e10228
+#define	DF_nWE		0x40e1022c
+#define	DF_nRE		0x40e10230
+
+#define	nXCVREN		0x40e10138
+
+#define	GPIO0		0x40e10124
+#define	GPIO1		0x40e10128
+#define	GPIO2		0x40e1012c
+#define	GPIO3		0x40e10130
+#define	GPIO4		0x40e10134
+#define	GPIO5		0x40e1028c
+#define	GPIO6		0x40e10290
+#define	GPIO7		0x40e10294
+#define	GPIO8		0x40e10298
+#define	GPIO9		0x40e1029c
+#define	GPIO10		0x40e10458
+#define	GPIO11		0x40e102a0
+#define	GPIO12		0x40e102a4
+#define	GPIO13		0x40e102a8
+#define	GPIO14		0x40e102ac
+#define	GPIO15		0x40e102b0
+#define	GPIO16		0x40e102b4
+#define	GPIO17		0x40e102b8
+#define	GPIO18		0x40e102bc
+#define	GPIO19		0x40e102c0
+#define	GPIO20		0x40e102c4
+#define	GPIO21		0x40e102c8
+#define	GPIO22		0x40e102cc
+#define	GPIO23		0x40e102d0
+#define	GPIO24		0x40e102d4
+#define	GPIO25		0x40e102d8
+#define	GPIO26		0x40e102dc
+
+#define	GPIO27		0x40e10400
+#define	GPIO28		0x40e10404
+#define	GPIO29		0x40e10408
+#define	GPIO30		0x40e1040c
+#define	GPIO31		0x40e10410
+#define	GPIO32		0x40e10414
+#define	GPIO33		0x40e10418
+#define	GPIO34		0x40e1041c
+#define	GPIO35		0x40e10420
+#define	GPIO36		0x40e10424
+#define	GPIO37		0x40e10428
+#define	GPIO38		0x40e1042c
+#define	GPIO39		0x40e10430
+#define	GPIO40		0x40e10434
+#define	GPIO41		0x40e10438
+#define	GPIO42		0x40e1043c
+#define	GPIO43		0x40e10440
+#define	GPIO44		0x40e10444
+#define	GPIO45		0x40e10448
+#define	GPIO46		0x40e1044c
+#define	GPIO47		0x40e10450
+#define	GPIO48		0x40e10454
+#define	GPIO49		0x40e1045c
+#define	GPIO50		0x40e10460
+#define	GPIO51		0x40e10464
+#define	GPIO52		0x40e10468
+#define	GPIO53		0x40e1046c
+#define	GPIO54		0x40e10470
+#define	GPIO55		0x40e10474
+#define	GPIO56		0x40e10478
+#define	GPIO57		0x40e1047c
+#define	GPIO58		0x40e10480
+#define	GPIO59		0x40e10484
+#define	GPIO60		0x40e10488
+#define	GPIO61		0x40e1048c
+#define	GPIO62		0x40e10490
+
+#define	GPIO6_2		0x40e10494
+#define	GPIO7_2		0x40e10498
+#define	GPIO8_2		0x40e1049c
+#define	GPIO9_2		0x40e104a0
+#define	GPIO10_2	0x40e104a4
+#define	GPIO11_2	0x40e104a8
+#define	GPIO12_2	0x40e104ac
+#define	GPIO13_2	0x40e104b0
+
+#define	GPIO63		0x40e104b4
+#define	GPIO64		0x40e104b8
+#define	GPIO65		0x40e104bc
+#define	GPIO66		0x40e104c0
+#define	GPIO67		0x40e104c4
+#define	GPIO68		0x40e104c8
+#define	GPIO69		0x40e104cc
+#define	GPIO70		0x40e104d0
+#define	GPIO71		0x40e104d4
+#define	GPIO72		0x40e104d8
+#define	GPIO73		0x40e104dc
+
+#define	GPIO14_2	0x40e104e0
+#define	GPIO15_2	0x40e104e4
+#define	GPIO16_2	0x40e104e8
+#define	GPIO17_2	0x40e104ec
+
+#define	GPIO74		0x40e104f0
+#define	GPIO75		0x40e104f4
+#define	GPIO76		0x40e104f8
+#define	GPIO77		0x40e104fc
+#define	GPIO78		0x40e10500
+#define	GPIO79		0x40e10504
+#define	GPIO80		0x40e10508
+#define	GPIO81		0x40e1050c
+#define	GPIO82		0x40e10510
+#define	GPIO83		0x40e10514
+#define	GPIO84		0x40e10518
+#define	GPIO85		0x40e1051c
+#define	GPIO86		0x40e10520
+#define	GPIO87		0x40e10524
+#define	GPIO88		0x40e10528
+#define	GPIO89		0x40e1052c
+#define	GPIO90		0x40e10530
+#define	GPIO91		0x40e10534
+#define	GPIO92		0x40e10538
+#define	GPIO93		0x40e1053c
+#define	GPIO94		0x40e10540
+#define	GPIO95		0x40e10544
+#define	GPIO96		0x40e10548
+#define	GPIO97		0x40e1054c
+#define	GPIO98		0x40e10550
+
+#define	GPIO99		0x40e10600
+#define	GPIO100		0x40e10604
+#define	GPIO101		0x40e10608
+#define	GPIO102		0x40e1060c
+#define	GPIO103		0x40e10610
+#define	GPIO104		0x40e10614
+#define	GPIO105		0x40e10618
+#define	GPIO106		0x40e1061c
+#define	GPIO107		0x40e10620
+#define	GPIO108		0x40e10624
+#define	GPIO109		0x40e10628
+#define	GPIO110		0x40e1062c
+#define	GPIO111		0x40e10630
+#define	GPIO112		0x40e10634
+
+#define	GPIO113		0x40e10638
+#define	GPIO114		0x40e1063c
+#define	GPIO115		0x40e10640
+#define	GPIO116		0x40e10644
+#define	GPIO117		0x40e10648
+#define	GPIO118		0x40e1064c
+#define	GPIO119		0x40e10650
+#define	GPIO120		0x40e10654
+#define	GPIO121		0x40e10658
+#define	GPIO122		0x40e1065c
+#define	GPIO123		0x40e10660
+#define	GPIO124		0x40e10664
+#define	GPIO125		0x40e10668
+#define	GPIO126		0x40e1066c
+#define	GPIO127		0x40e10670
+
+#define	GPIO0_2		0x40e10674
+#define	GPIO1_2		0x40e10678
+#define	GPIO2_2		0x40e1067c
+#define	GPIO3_2		0x40e10680
+#define	GPIO4_2		0x40e10684
+#define	GPIO5_2		0x40e10688
+
+/* PXA300 and PXA310 */
+#elif	defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310)
+#define	DF_IO0		0x40e10220
+#define	DF_IO1		0x40e10228
+#define	DF_IO2		0x40e10230
+#define	DF_IO3		0x40e10238
+#define	DF_IO4		0x40e10258
+#define	DF_IO5		0x40e10260
+#define	DF_IO7		0x40e10270
+#define	DF_IO6		0x40e10268
+#define	DF_IO8		0x40e10224
+#define	DF_IO9		0x40e1022c
+#define	DF_IO10		0x40e10234
+#define	DF_IO11		0x40e1023c
+#define	DF_IO12		0x40e1025c
+#define	DF_IO13		0x40e10264
+#define	DF_IO14		0x40e1026c
+#define	DF_IO15		0x40e10274
+#define	DF_CLE_NOE	0x40e10240
+#define	DF_ALE_nWE	0x40e1020c
+#define	DF_SCLK_E	0x40e10250
+#define	nCS0		0x40e100c4
+#define	nCS1		0x40e100c0
+#define	nBE0		0x40e10204
+#define	nBE1		0x40e10208
+#define	nLUA		0x40e10244
+#define	nLLA		0x40e10254
+#define	DF_ADDR0	0x40e10210
+#define	DF_ADDR1	0x40e10214
+#define	DF_ADDR2	0x40e10218
+#define	DF_ADDR3	0x40e1021c
+#define	DF_INT_RnB	0x40e100c8
+#define	DF_nCS0		0x40e10248
+#define	DF_nCS1		0x40e10278
+#define	DF_nWE		0x40e100cc
+#define	DF_nRE		0x40e10200
+
+#define	GPIO0		0x40e100b4
+#define	GPIO1		0x40e100b8
+#define	GPIO2		0x40e100bc
+#define	GPIO3		0x40e1027c
+#define	GPIO4		0x40e10280
+
+#define	GPIO5		0x40e10284
+#define	GPIO6		0x40e10288
+#define	GPIO7		0x40e1028c
+#define	GPIO8		0x40e10290
+#define	GPIO9		0x40e10294
+#define	GPIO10		0x40e10298
+#define	GPIO11		0x40e1029c
+#define	GPIO12		0x40e102a0
+#define	GPIO13		0x40e102a4
+#define	GPIO14		0x40e102a8
+#define	GPIO15		0x40e102ac
+#define	GPIO16		0x40e102b0
+#define	GPIO17		0x40e102b4
+#define	GPIO18		0x40e102b8
+#define	GPIO19		0x40e102bc
+#define	GPIO20		0x40e102c0
+#define	GPIO21		0x40e102c4
+#define	GPIO22		0x40e102c8
+#define	GPIO23		0x40e102cc
+#define	GPIO24		0x40e102d0
+#define	GPIO25		0x40e102d4
+#define	GPIO26		0x40e102d8
+
+#define	GPIO27		0x40e10400
+#define	GPIO28		0x40e10404
+#define	GPIO29		0x40e10408
+#define	ULPI_STP	0x40e1040c
+#define	ULPI_NXT	0x40e10410
+#define	ULPI_DIR	0x40e10414
+#define	GPIO30		0x40e10418
+#define	GPIO31		0x40e1041c
+#define	GPIO32		0x40e10420
+#define	GPIO33		0x40e10424
+#define	GPIO34		0x40e10428
+#define	GPIO35		0x40e1042c
+#define	GPIO36		0x40e10430
+#define	GPIO37		0x40e10434
+#define	GPIO38		0x40e10438
+#define	GPIO39		0x40e1043c
+#define	GPIO40		0x40e10440
+#define	GPIO41		0x40e10444
+#define	GPIO42		0x40e10448
+#define	GPIO43		0x40e1044c
+#define	GPIO44		0x40e10450
+#define	GPIO45		0x40e10454
+#define	GPIO46		0x40e10458
+#define	GPIO47		0x40e1045c
+#define	GPIO48		0x40e10460
+
+#define	GPIO49		0x40e10464
+#define	GPIO50		0x40e10468
+#define	GPIO51		0x40e1046c
+#define	GPIO52		0x40e10470
+#define	GPIO53		0x40e10474
+#define	GPIO54		0x40e10478
+#define	GPIO55		0x40e1047c
+#define	GPIO56		0x40e10480
+#define	GPIO57		0x40e10484
+#define	GPIO58		0x40e10488
+#define	GPIO59		0x40e1048c
+#define	GPIO60		0x40e10490
+#define	GPIO61		0x40e10494
+#define	GPIO62		0x40e10498
+#define	GPIO63		0x40e1049c
+#define	GPIO64		0x40e104a0
+#define	GPIO65		0x40e104a4
+#define	GPIO66		0x40e104a8
+#define	GPIO67		0x40e104ac
+#define	GPIO68		0x40e104b0
+#define	GPIO69		0x40e104b4
+#define	GPIO70		0x40e104b8
+#define	GPIO71		0x40e104bc
+#define	GPIO72		0x40e104c0
+#define	GPIO73		0x40e104c4
+#define	GPIO74		0x40e104c8
+#define	GPIO75		0x40e104cc
+#define	GPIO76		0x40e104d0
+#define	GPIO77		0x40e104d4
+#define	GPIO78		0x40e104d8
+#define	GPIO79		0x40e104dc
+#define	GPIO80		0x40e104e0
+#define	GPIO81		0x40e104e4
+#define	GPIO82		0x40e104e8
+#define	GPIO83		0x40e104ec
+#define	GPIO84		0x40e104f0
+#define	GPIO85		0x40e104f4
+#define	GPIO86		0x40e104f8
+#define	GPIO87		0x40e104fc
+#define	GPIO88		0x40e10500
+#define	GPIO89		0x40e10504
+#define	GPIO90		0x40e10508
+#define	GPIO91		0x40e1050c
+#define	GPIO92		0x40e10510
+#define	GPIO93		0x40e10514
+#define	GPIO94		0x40e10518
+#define	GPIO95		0x40e1051c
+#define	GPIO96		0x40e10520
+#define	GPIO97		0x40e10524
+#define	GPIO98		0x40e10528
+
+#define	GPIO99		0x40e10600
+#define	GPIO100		0x40e10604
+#define	GPIO101		0x40e10608
+#define	GPIO102		0x40e1060c
+#define	GPIO103		0x40e10610
+#define	GPIO104		0x40e10614
+#define	GPIO105		0x40e10618
+#define	GPIO106		0x40e1061c
+#define	GPIO107		0x40e10620
+#define	GPIO108		0x40e10624
+#define	GPIO109		0x40e10628
+#define	GPIO110		0x40e1062c
+#define	GPIO111		0x40e10630
+#define	GPIO112		0x40e10634
+
+#define	GPIO113		0x40e10638
+#define	GPIO114		0x40e1063c
+#define	GPIO115		0x40e10640
+#define	GPIO116		0x40e10644
+#define	GPIO117		0x40e10648
+#define	GPIO118		0x40e1064c
+#define	GPIO119		0x40e10650
+#define	GPIO120		0x40e10654
+#define	GPIO121		0x40e10658
+#define	GPIO122		0x40e1065c
+#define	GPIO123		0x40e10660
+#define	GPIO124		0x40e10664
+#define	GPIO125		0x40e10668
+#define	GPIO126		0x40e1066c
+#define	GPIO127		0x40e10670
+
+#define	GPIO0_2		0x40e10674
+#define	GPIO1_2		0x40e10678
+#define	GPIO2_2		0x40e102dc
+#define	GPIO3_2		0x40e102e0
+#define	GPIO4_2		0x40e102e4
+#define	GPIO5_2		0x40e102e8
+#define	GPIO6_2		0x40e102ec
+
+#ifndef	CONFIG_CPU_PXA300	/* PXA310 only */
+#define	GPIO7_2		0x40e1052c
+#define	GPIO8_2		0x40e10530
+#define	GPIO9_2		0x40e10534
+#define	GPIO10_2	0x40e10538
+#endif
+#endif
 
+#ifdef CONFIG_CPU_MONAHANS
 /* MFPR Bit Definitions, see 4-10, Vol. 1 */
 #define PULL_SEL	0x8000
 #define PULLUP_EN	0x4000
@@ -1470,62 +1854,8 @@ typedef void		(*ExcpHndlr) (void) ;
 #define AF_SEL_6	0x6	/* Alternate function 6 */
 #define AF_SEL_7	0x7	/* Alternate function 7 */
 
-
-#else /* CONFIG_CPU_MONAHANS */
-
-#define GAFR0_L		__REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
-#define GAFR0_U		__REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
-#define GAFR1_L		__REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
-#define GAFR1_U		__REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
-#define GAFR2_L		__REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
-#define GAFR2_U		__REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO 80 */
 #endif /* CONFIG_CPU_MONAHANS */
 
-/* More handy macros.  The argument is a literal GPIO number. */
-
-#define GPIO_bit(x)	(1 << ((x) & 0x1f))
-
-#ifdef CONFIG_PXA27X
-
-/* Interrupt Controller */
-
-#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
-#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
-#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
-
-#define _GPLR(x)	__REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define _GPDR(x)	__REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define _GPSR(x)	__REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define _GPCR(x)	__REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define _GRER(x)	__REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define _GFER(x)	__REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define _GEDR(x)	__REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define _GAFR(x)	__REG2(0x40E00054, ((x) & 0x70) >> 2)
-
-#define GPLR(x)		(*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
-#define GPDR(x)		(*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
-#define GPSR(x)		(*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
-#define GPCR(x)		(*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
-#define GRER(x)		(*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
-#define GFER(x)		(*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
-#define GEDR(x)		(*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
-#define GAFR(x)		(*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
-			((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
-#else
-
-#define GPLR(x)		__REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define GPDR(x)		__REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define GPSR(x)		__REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define GPCR(x)		__REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define GRER(x)		__REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define GFER(x)		__REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define GEDR(x)		__REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define GAFR(x)		__REG2(0x40E00054, ((x) & 0x70) >> 2)
-
-#endif
-
 /* GPIO alternate function assignments */
 
 #define GPIO1_RST		1	/* reset */
@@ -1732,63 +2062,63 @@ typedef void		(*ExcpHndlr) (void) ;
  */
 #ifdef CONFIG_CPU_MONAHANS
 
-#define ASCR		__REG(0x40F40000)  /* Application Subsystem Power Status/Control Register */
-#define ARSR		__REG(0x40F40004)  /* Application Subsystem Reset Status Register */
-#define AD3ER		__REG(0x40F40008)  /* Application Subsystem D3 state Wakeup Enable Register */
-#define AD3SR		__REG(0x40F4000C)  /* Application Subsystem D3 state Wakeup Status Register */
-#define AD2D0ER		__REG(0x40F40010)  /* Application Subsystem D2 to D0 state Wakeup Enable Register */
-#define AD2D0SR		__REG(0x40F40014)  /* Application Subsystem D2 to D0 state Wakeup Status Register */
-#define AD2D1ER		__REG(0x40F40018)  /* Application Subsystem D2 to D1 state Wakeup Enable Register */
-#define AD2D1SR		__REG(0x40F4001C)  /* Application Subsystem D2 to D1 state Wakeup Status Register */
-#define AD1D0ER		__REG(0x40F40020)  /* Application Subsystem D1 to D0 state Wakeup Enable Register */
-#define AD1D0SR		__REG(0x40F40024)  /* Application Subsystem D1 to D0 state Wakeup Status Register */
-#define ASDCNT		__REG(0x40F40028)  /* Application Subsystem SRAM Drowsy Count Register */
-#define AD3R		__REG(0x40F40030)  /* Application Subsystem D3 State Configuration Register */
-#define AD2R		__REG(0x40F40034)  /* Application Subsystem D2 State Configuration Register */
-#define AD1R		__REG(0x40F40038)  /* Application Subsystem D1 State Configuration Register */
-
-#define PMCR		__REG(0x40F50000)  /* Power Manager Control Register */
-#define PSR		__REG(0x40F50004)  /* Power Manager S2 Status Register */
-#define PSPR		__REG(0x40F50008)  /* Power Manager Scratch Pad Register */
-#define PCFR		__REG(0x40F5000C)  /* Power Manager General Configuration Register */
-#define PWER		__REG(0x40F50010)  /* Power Manager Wake-up Enable Register */
-#define PWSR		__REG(0x40F50014)  /* Power Manager Wake-up Status Register */
-#define PECR		__REG(0x40F50018)  /* Power Manager EXT_WAKEUP[1:0] Control Register */
-#define DCDCSR		__REG(0x40F50080)  /* DC-DC Controller Status Register */
-#define PVCR		__REG(0x40F50100)  /* Power Manager Voltage Change Control Register */
-#define    PCMD(x) __REG(0x40F50110 + x*4)
-#define    PCMD0   __REG(0x40F50110 + 0 * 4)
-#define    PCMD1   __REG(0x40F50110 + 1 * 4)
-#define    PCMD2   __REG(0x40F50110 + 2 * 4)
-#define    PCMD3   __REG(0x40F50110 + 3 * 4)
-#define    PCMD4   __REG(0x40F50110 + 4 * 4)
-#define    PCMD5   __REG(0x40F50110 + 5 * 4)
-#define    PCMD6   __REG(0x40F50110 + 6 * 4)
-#define    PCMD7   __REG(0x40F50110 + 7 * 4)
-#define    PCMD8   __REG(0x40F50110 + 8 * 4)
-#define    PCMD9   __REG(0x40F50110 + 9 * 4)
-#define    PCMD10  __REG(0x40F50110 + 10 * 4)
-#define    PCMD11  __REG(0x40F50110 + 11 * 4)
-#define    PCMD12  __REG(0x40F50110 + 12 * 4)
-#define    PCMD13  __REG(0x40F50110 + 13 * 4)
-#define    PCMD14  __REG(0x40F50110 + 14 * 4)
-#define    PCMD15  __REG(0x40F50110 + 15 * 4)
-#define    PCMD16  __REG(0x40F50110 + 16 * 4)
-#define    PCMD17  __REG(0x40F50110 + 17 * 4)
-#define    PCMD18  __REG(0x40F50110 + 18 * 4)
-#define    PCMD19  __REG(0x40F50110 + 19 * 4)
-#define    PCMD20  __REG(0x40F50110 + 20 * 4)
-#define    PCMD21  __REG(0x40F50110 + 21 * 4)
-#define    PCMD22  __REG(0x40F50110 + 22 * 4)
-#define    PCMD23  __REG(0x40F50110 + 23 * 4)
-#define    PCMD24  __REG(0x40F50110 + 24 * 4)
-#define    PCMD25  __REG(0x40F50110 + 25 * 4)
-#define    PCMD26  __REG(0x40F50110 + 26 * 4)
-#define    PCMD27  __REG(0x40F50110 + 27 * 4)
-#define    PCMD28  __REG(0x40F50110 + 28 * 4)
-#define    PCMD29  __REG(0x40F50110 + 29 * 4)
-#define    PCMD30  __REG(0x40F50110 + 30 * 4)
-#define    PCMD31  __REG(0x40F50110 + 31 * 4)
+#define ASCR		0x40F40000  /* Application Subsystem Power Status/Control Register */
+#define ARSR		0x40F40004  /* Application Subsystem Reset Status Register */
+#define AD3ER		0x40F40008  /* Application Subsystem D3 state Wakeup Enable Register */
+#define AD3SR		0x40F4000C  /* Application Subsystem D3 state Wakeup Status Register */
+#define AD2D0ER		0x40F40010  /* Application Subsystem D2 to D0 state Wakeup Enable Register */
+#define AD2D0SR		0x40F40014  /* Application Subsystem D2 to D0 state Wakeup Status Register */
+#define AD2D1ER		0x40F40018  /* Application Subsystem D2 to D1 state Wakeup Enable Register */
+#define AD2D1SR		0x40F4001C  /* Application Subsystem D2 to D1 state Wakeup Status Register */
+#define AD1D0ER		0x40F40020  /* Application Subsystem D1 to D0 state Wakeup Enable Register */
+#define AD1D0SR		0x40F40024  /* Application Subsystem D1 to D0 state Wakeup Status Register */
+#define ASDCNT		0x40F40028  /* Application Subsystem SRAM Drowsy Count Register */
+#define AD3R		0x40F40030  /* Application Subsystem D3 State Configuration Register */
+#define AD2R		0x40F40034  /* Application Subsystem D2 State Configuration Register */
+#define AD1R		0x40F40038  /* Application Subsystem D1 State Configuration Register */
+
+#define PMCR		0x40F50000  /* Power Manager Control Register */
+#define PSR		0x40F50004  /* Power Manager S2 Status Register */
+#define PSPR		0x40F50008  /* Power Manager Scratch Pad Register */
+#define PCFR		0x40F5000C  /* Power Manager General Configuration Register */
+#define PWER		0x40F50010  /* Power Manager Wake-up Enable Register */
+#define PWSR		0x40F50014  /* Power Manager Wake-up Status Register */
+#define PECR		0x40F50018  /* Power Manager EXT_WAKEUP[1:0] Control Register */
+#define DCDCSR		0x40F50080  /* DC-DC Controller Status Register */
+#define PVCR		0x40F50100  /* Power Manager Voltage Change Control Register */
+#define    PCMD(x) (0x40F50110 + x*4)
+#define    PCMD0   (0x40F50110 + 0 * 4)
+#define    PCMD1   (0x40F50110 + 1 * 4)
+#define    PCMD2   (0x40F50110 + 2 * 4)
+#define    PCMD3   (0x40F50110 + 3 * 4)
+#define    PCMD4   (0x40F50110 + 4 * 4)
+#define    PCMD5   (0x40F50110 + 5 * 4)
+#define    PCMD6   (0x40F50110 + 6 * 4)
+#define    PCMD7   (0x40F50110 + 7 * 4)
+#define    PCMD8   (0x40F50110 + 8 * 4)
+#define    PCMD9   (0x40F50110 + 9 * 4)
+#define    PCMD10  (0x40F50110 + 10 * 4)
+#define    PCMD11  (0x40F50110 + 11 * 4)
+#define    PCMD12  (0x40F50110 + 12 * 4)
+#define    PCMD13  (0x40F50110 + 13 * 4)
+#define    PCMD14  (0x40F50110 + 14 * 4)
+#define    PCMD15  (0x40F50110 + 15 * 4)
+#define    PCMD16  (0x40F50110 + 16 * 4)
+#define    PCMD17  (0x40F50110 + 17 * 4)
+#define    PCMD18  (0x40F50110 + 18 * 4)
+#define    PCMD19  (0x40F50110 + 19 * 4)
+#define    PCMD20  (0x40F50110 + 20 * 4)
+#define    PCMD21  (0x40F50110 + 21 * 4)
+#define    PCMD22  (0x40F50110 + 22 * 4)
+#define    PCMD23  (0x40F50110 + 23 * 4)
+#define    PCMD24  (0x40F50110 + 24 * 4)
+#define    PCMD25  (0x40F50110 + 25 * 4)
+#define    PCMD26  (0x40F50110 + 26 * 4)
+#define    PCMD27  (0x40F50110 + 27 * 4)
+#define    PCMD28  (0x40F50110 + 28 * 4)
+#define    PCMD29  (0x40F50110 + 29 * 4)
+#define    PCMD30  (0x40F50110 + 30 * 4)
+#define    PCMD31  (0x40F50110 + 31 * 4)
 
 #define    PCMD_MBC    (1<<12)
 #define    PCMD_DCE    (1<<11)
@@ -1798,64 +2128,64 @@ typedef void		(*ExcpHndlr) (void) ;
 #define PVCR_FVC                   (0x1 << 28)
 #define PVCR_VCSA                  (0x1<<14)
 #define PVCR_CommandDelay          (0xf80)
-#define PVCR_ReadPointer           (0x01f00000)
+#define PVCR_ReadPointer           0x01f00000
 #define PVCR_SlaveAddress          (0x7f)
 
 #else /* ifdef CONFIG_CPU_MONAHANS */
 
-#define PMCR		__REG(0x40F00000)  /* Power Manager Control Register */
-#define PSSR		__REG(0x40F00004)  /* Power Manager Sleep Status Register */
-#define PSPR		__REG(0x40F00008)  /* Power Manager Scratch Pad Register */
-#define PWER		__REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
-#define PRER		__REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER		__REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR		__REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR		__REG(0x40F0001C)  /* Power Manager General Configuration Register */
-#define PGSR0		__REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1		__REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2		__REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3		__REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR		__REG(0x40F00030)  /* Reset Controller Status Register */
-
-#define	   PSLR	   __REG(0x40F00034)	/* Power Manager Sleep Config Register */
-#define	   PSTR	   __REG(0x40F00038)	/* Power Manager Standby Config Register */
-#define	   PSNR	   __REG(0x40F0003C)	/* Power Manager Sense Config Register */
-#define	   PVCR	   __REG(0x40F00040)	/* Power Manager VoltageControl Register */
-#define	   PKWR	   __REG(0x40F00050)	/* Power Manager KB Wake-up Enable Reg */
-#define	   PKSR	   __REG(0x40F00054)	/* Power Manager KB Level-Detect Register */
-#define	   PCMD(x) __REG(0x40F00080 + x*4)
-#define	   PCMD0   __REG(0x40F00080 + 0 * 4)
-#define	   PCMD1   __REG(0x40F00080 + 1 * 4)
-#define	   PCMD2   __REG(0x40F00080 + 2 * 4)
-#define	   PCMD3   __REG(0x40F00080 + 3 * 4)
-#define	   PCMD4   __REG(0x40F00080 + 4 * 4)
-#define	   PCMD5   __REG(0x40F00080 + 5 * 4)
-#define	   PCMD6   __REG(0x40F00080 + 6 * 4)
-#define	   PCMD7   __REG(0x40F00080 + 7 * 4)
-#define	   PCMD8   __REG(0x40F00080 + 8 * 4)
-#define	   PCMD9   __REG(0x40F00080 + 9 * 4)
-#define	   PCMD10  __REG(0x40F00080 + 10 * 4)
-#define	   PCMD11  __REG(0x40F00080 + 11 * 4)
-#define	   PCMD12  __REG(0x40F00080 + 12 * 4)
-#define	   PCMD13  __REG(0x40F00080 + 13 * 4)
-#define	   PCMD14  __REG(0x40F00080 + 14 * 4)
-#define	   PCMD15  __REG(0x40F00080 + 15 * 4)
-#define	   PCMD16  __REG(0x40F00080 + 16 * 4)
-#define	   PCMD17  __REG(0x40F00080 + 17 * 4)
-#define	   PCMD18  __REG(0x40F00080 + 18 * 4)
-#define	   PCMD19  __REG(0x40F00080 + 19 * 4)
-#define	   PCMD20  __REG(0x40F00080 + 20 * 4)
-#define	   PCMD21  __REG(0x40F00080 + 21 * 4)
-#define	   PCMD22  __REG(0x40F00080 + 22 * 4)
-#define	   PCMD23  __REG(0x40F00080 + 23 * 4)
-#define	   PCMD24  __REG(0x40F00080 + 24 * 4)
-#define	   PCMD25  __REG(0x40F00080 + 25 * 4)
-#define	   PCMD26  __REG(0x40F00080 + 26 * 4)
-#define	   PCMD27  __REG(0x40F00080 + 27 * 4)
-#define	   PCMD28  __REG(0x40F00080 + 28 * 4)
-#define	   PCMD29  __REG(0x40F00080 + 29 * 4)
-#define	   PCMD30  __REG(0x40F00080 + 30 * 4)
-#define	   PCMD31  __REG(0x40F00080 + 31 * 4)
+#define PMCR		0x40F00000  /* Power Manager Control Register */
+#define PSSR		0x40F00004  /* Power Manager Sleep Status Register */
+#define PSPR		0x40F00008  /* Power Manager Scratch Pad Register */
+#define PWER		0x40F0000C  /* Power Manager Wake-up Enable Register */
+#define PRER		0x40F00010  /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER		0x40F00014  /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR		0x40F00018  /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR		0x40F0001C  /* Power Manager General Configuration Register */
+#define PGSR0		0x40F00020  /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1		0x40F00024  /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2		0x40F00028  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3		0x40F0002C  /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR		0x40F00030  /* Reset Controller Status Register */
+
+#define	   PSLR	   0x40F00034	/* Power Manager Sleep Config Register */
+#define	   PSTR	   0x40F00038	/* Power Manager Standby Config Register */
+#define	   PSNR	   0x40F0003C	/* Power Manager Sense Config Register */
+#define	   PVCR	   0x40F00040	/* Power Manager VoltageControl Register */
+#define	   PKWR	   0x40F00050	/* Power Manager KB Wake-up Enable Reg */
+#define	   PKSR	   0x40F00054	/* Power Manager KB Level-Detect Register */
+#define	   PCMD(x) (0x40F00080 + x*4)
+#define	   PCMD0   (0x40F00080 + 0 * 4)
+#define	   PCMD1   (0x40F00080 + 1 * 4)
+#define	   PCMD2   (0x40F00080 + 2 * 4)
+#define	   PCMD3   (0x40F00080 + 3 * 4)
+#define	   PCMD4   (0x40F00080 + 4 * 4)
+#define	   PCMD5   (0x40F00080 + 5 * 4)
+#define	   PCMD6   (0x40F00080 + 6 * 4)
+#define	   PCMD7   (0x40F00080 + 7 * 4)
+#define	   PCMD8   (0x40F00080 + 8 * 4)
+#define	   PCMD9   (0x40F00080 + 9 * 4)
+#define	   PCMD10  (0x40F00080 + 10 * 4)
+#define	   PCMD11  (0x40F00080 + 11 * 4)
+#define	   PCMD12  (0x40F00080 + 12 * 4)
+#define	   PCMD13  (0x40F00080 + 13 * 4)
+#define	   PCMD14  (0x40F00080 + 14 * 4)
+#define	   PCMD15  (0x40F00080 + 15 * 4)
+#define	   PCMD16  (0x40F00080 + 16 * 4)
+#define	   PCMD17  (0x40F00080 + 17 * 4)
+#define	   PCMD18  (0x40F00080 + 18 * 4)
+#define	   PCMD19  (0x40F00080 + 19 * 4)
+#define	   PCMD20  (0x40F00080 + 20 * 4)
+#define	   PCMD21  (0x40F00080 + 21 * 4)
+#define	   PCMD22  (0x40F00080 + 22 * 4)
+#define	   PCMD23  (0x40F00080 + 23 * 4)
+#define	   PCMD24  (0x40F00080 + 24 * 4)
+#define	   PCMD25  (0x40F00080 + 25 * 4)
+#define	   PCMD26  (0x40F00080 + 26 * 4)
+#define	   PCMD27  (0x40F00080 + 27 * 4)
+#define	   PCMD28  (0x40F00080 + 28 * 4)
+#define	   PCMD29  (0x40F00080 + 29 * 4)
+#define	   PCMD30  (0x40F00080 + 30 * 4)
+#define	   PCMD31  (0x40F00080 + 31 * 4)
 
 #define	   PCMD_MBC    (1<<12)
 #define	   PCMD_DCE    (1<<11)
@@ -1891,183 +2221,58 @@ typedef void		(*ExcpHndlr) (void) ;
 /*
  * SSP Serial Port Registers
  */
-#define SSCR0		__REG(0x41000000)  /* SSP Control Register 0 */
-#define SSCR1		__REG(0x41000004)  /* SSP Control Register 1 */
-#define SSSR		__REG(0x41000008)  /* SSP Status Register */
-#define SSITR		__REG(0x4100000C)  /* SSP Interrupt Test Register */
-#define SSDR		__REG(0x41000010)  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
+#define SSCR0		0x41000000  /* SSP Control Register 0 */
+#define SSCR1		0x41000004  /* SSP Control Register 1 */
+#define SSSR		0x41000008  /* SSP Status Register */
+#define SSITR		0x4100000C  /* SSP Interrupt Test Register */
+#define SSDR		0x41000010  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
 
 /*
  * MultiMediaCard (MMC) controller
  */
-#define MMC_STRPCL	__REG(0x41100000)  /* Control to start and stop MMC clock */
-#define MMC_STAT	__REG(0x41100004)  /* MMC Status Register (read only) */
-#define MMC_CLKRT	__REG(0x41100008)  /* MMC clock rate */
-#define MMC_SPI		__REG(0x4110000c)  /* SPI mode control bits */
-#define MMC_CMDAT	__REG(0x41100010)  /* Command/response/data sequence control */
-#define MMC_RESTO	__REG(0x41100014)  /* Expected response time out */
-#define MMC_RDTO	__REG(0x41100018)  /* Expected data read time out */
-#define MMC_BLKLEN	__REG(0x4110001c)  /* Block length of data transaction */
-#define MMC_NOB		__REG(0x41100020)  /* Number of blocks, for block mode */
-#define MMC_PRTBUF	__REG(0x41100024)  /* Partial MMC_TXFIFO FIFO written */
-#define MMC_I_MASK	__REG(0x41100028)  /* Interrupt Mask */
-#define MMC_I_REG	__REG(0x4110002c)  /* Interrupt Register (read only) */
-#define MMC_CMD		__REG(0x41100030)  /* Index of current command */
-#define MMC_ARGH	__REG(0x41100034)  /* MSW part of the current command argument */
-#define MMC_ARGL	__REG(0x41100038)  /* LSW part of the current command argument */
-#define MMC_RES		__REG(0x4110003c)  /* Response FIFO (read only) */
-#define MMC_RXFIFO	__REG(0x41100040)  /* Receive FIFO (read only) */
-#define MMC_TXFIFO	__REG(0x41100044)  /* Transmit FIFO (write only) */
-
-/*
- * Core Clock
- */
-
-#if defined(CONFIG_CPU_MONAHANS)
-#define ACCR		__REG(0x41340000)  /* Application Subsystem Clock Configuration Register */
-#define ACSR		__REG(0x41340004)  /* Application Subsystem Clock Status Register */
-#define AICSR		__REG(0x41340008)  /* Application Subsystem Interrupt Control/Status Register */
-#define CKENA		__REG(0x4134000C)  /* A Clock Enable Register */
-#define CKENB		__REG(0x41340010)  /* B Clock Enable Register */
-#define AC97_DIV	__REG(0x41340014)  /* AC97 clock divisor value register */
-
-#define ACCR_SMC_MASK	0x03800000	/* Static Memory Controller Frequency Select */
-#define ACCR_SRAM_MASK	0x000c0000	/* SRAM Controller Frequency Select */
-#define ACCR_FC_MASK	0x00030000	/* Frequency Change Frequency Select */
-#define ACCR_HSIO_MASK	0x0000c000	/* High Speed IO Frequency Select */
-#define ACCR_DDR_MASK	0x00003000	/* DDR Memory Controller Frequency Select */
-#define ACCR_XN_MASK	0x00000700	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define ACCR_XL_MASK	0x0000001f	/* Crystal Frequency to Memory Frequency Multiplier */
-#define ACCR_XPDIS	(1 << 31)
-#define ACCR_SPDIS	(1 << 30)
-#define ACCR_13MEND1	(1 << 27)
-#define ACCR_D0CS	(1 << 26)
-#define ACCR_13MEND2	(1 << 21)
-#define ACCR_PCCE	(1 << 11)
-
-#define CKENA_30_MSL0	(1 << 30)	/* MSL0 Interface Unit Clock Enable */
-#define CKENA_29_SSP4	(1 << 29)	/* SSP3 Unit Clock Enable */
-#define CKENA_28_SSP3	(1 << 28)	/* SSP2 Unit Clock Enable */
-#define CKENA_27_SSP2	(1 << 27)	/* SSP1 Unit Clock Enable */
-#define CKENA_26_SSP1	(1 << 26)	/* SSP0 Unit Clock Enable */
-#define CKENA_25_TSI	(1 << 25)	/* TSI Clock Enable */
-#define CKENA_24_AC97	(1 << 24)	/* AC97 Unit Clock Enable */
-#define CKENA_23_STUART	(1 << 23)	/* STUART Unit Clock Enable */
-#define CKENA_22_FFUART	(1 << 22)	/* FFUART Unit Clock Enable */
-#define CKENA_21_BTUART	(1 << 21)	/* BTUART Unit Clock Enable */
-#define CKENA_20_UDC	(1 << 20)	/* UDC Clock Enable */
-#define CKENA_19_TPM	(1 << 19)	/* TPM Unit Clock Enable */
-#define CKENA_18_USIM1	(1 << 18)	/* USIM1 Unit Clock Enable */
-#define CKENA_17_USIM0	(1 << 17)	/* USIM0 Unit Clock Enable */
-#define CKENA_15_CIR	(1 << 15)	/* Consumer IR Clock Enable */
-#define CKENA_14_KEY	(1 << 14)	/* Keypad Controller Clock Enable */
-#define CKENA_13_MMC1	(1 << 13)	/* MMC1 Clock Enable */
-#define CKENA_12_MMC0	(1 << 12)	/* MMC0 Clock Enable */
-#define CKENA_11_FLASH	(1 << 11)	/* Boot ROM Clock Enable */
-#define CKENA_10_SRAM	(1 << 10)	/* SRAM Controller Clock Enable */
-#define CKENA_9_SMC	(1 << 9)	/* Static Memory Controller */
-#define CKENA_8_DMC	(1 << 8)	/* Dynamic Memory Controller */
-#define CKENA_7_GRAPHICS (1 << 7)	/* 2D Graphics Clock Enable */
-#define CKENA_6_USBCLI	(1 << 6)	/* USB Client Unit Clock Enable */
-#define CKENA_4_NAND	(1 << 4)	/* NAND Flash Controller Clock Enable */
-#define CKENA_3_CAMERA	(1 << 3)	/* Camera Interface Clock Enable */
-#define CKENA_2_USBHOST	(1 << 2)	/* USB Host Unit Clock Enable */
-#define CKENA_1_LCD	(1 << 1)	/* LCD Unit Clock Enable */
-
-#define CKENB_9_SYSBUS2	(1 << 9)	/* System bus 2 */
-#define CKENB_8_1WIRE	(1 << 8)	/* One Wire Interface Unit Clock Enable */
-#define CKENB_7_GPIO	(1 << 7)	/* GPIO Clock Enable */
-#define CKENB_6_IRQ	(1 << 6)	/* Interrupt Controller Clock Enable */
-#define CKENB_4_I2C	(1 << 4)	/* I2C Unit Clock Enable */
-#define CKENB_1_PWM1	(1 << 1)	/* PWM2 & PWM3 Clock Enable */
-#define CKENB_0_PWM0	(1 << 0)	/* PWM0 & PWM1 Clock Enable */
-
-#else /* if defined CONFIG_CPU_MONAHANS */
-
-#define CCCR		__REG(0x41300000)  /* Core Clock Configuration Register */
-#define CKEN		__REG(0x41300004)  /* Clock Enable Register */
-#define OSCC		__REG(0x41300008)  /* Oscillator Configuration Register */
-
-#define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#if !defined(CONFIG_PXA27X)
-#define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
-#endif
-#define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
-
-#define CKEN24_CAMERA	(1 << 24)	/* Camera Interface Clock Enable */
-#define CKEN23_SSP1	(1 << 23)	/* SSP1 Unit Clock Enable */
-#define CKEN22_MEMC	(1 << 22)	/* Memory Controller Clock Enable */
-#define CKEN21_MEMSTK	(1 << 21)	/* Memory Stick Host Controller */
-#define CKEN20_IM	(1 << 20)	/* Internal Memory Clock Enable */
-#define CKEN19_KEYPAD	(1 << 19)	/* Keypad Interface Clock Enable */
-#define CKEN18_USIM	(1 << 18)	/* USIM Unit Clock Enable */
-#define CKEN17_MSL	(1 << 17)	/* MSL Unit Clock Enable */
-#define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */
-#define CKEN15_PWRI2C	(1 << 15)	/* PWR I2C Unit Clock Enable */
-#define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */
-#define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
-#define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
-#define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
-#if defined(CONFIG_PXA27X)
-#define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
-#define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
-#endif
-#define CKEN8_I2S	(1 << 8)	/* I2S Unit Clock Enable */
-#define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
-#define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
-#define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */
-#define CKEN3_SSP	(1 << 3)	/* SSP Unit Clock Enable */
-#define CKEN2_AC97	(1 << 2)	/* AC97 Unit Clock Enable */
-#define CKEN1_PWM1	(1 << 1)	/* PWM1 Clock Enable */
-#define CKEN0_PWM0	(1 << 0)	/* PWM0 Clock Enable */
-
-#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
-
-#if !defined(CONFIG_PXA27X)
-#define	 CCCR_L09      (0x1F)
-#define	 CCCR_L27      (0x1)
-#define	 CCCR_L32      (0x2)
-#define	 CCCR_L36      (0x3)
-#define	 CCCR_L40      (0x4)
-#define	 CCCR_L45      (0x5)
-
-#define	 CCCR_M1       (0x1 << 5)
-#define	 CCCR_M2       (0x2 << 5)
-#define	 CCCR_M4       (0x3 << 5)
-
-#define	 CCCR_N10      (0x2 << 7)
-#define	 CCCR_N15      (0x3 << 7)
-#define	 CCCR_N20      (0x4 << 7)
-#define	 CCCR_N25      (0x5 << 7)
-#define	 CCCR_N30      (0x6 << 7)
-#endif
+#define MMC_STRPCL	0x41100000  /* Control to start and stop MMC clock */
+#define MMC_STAT	0x41100004  /* MMC Status Register (read only) */
+#define MMC_CLKRT	0x41100008  /* MMC clock rate */
+#define MMC_SPI		0x4110000c  /* SPI mode control bits */
+#define MMC_CMDAT	0x41100010  /* Command/response/data sequence control */
+#define MMC_RESTO	0x41100014  /* Expected response time out */
+#define MMC_RDTO	0x41100018  /* Expected data read time out */
+#define MMC_BLKLEN	0x4110001c  /* Block length of data transaction */
+#define MMC_NOB		0x41100020  /* Number of blocks, for block mode */
+#define MMC_PRTBUF	0x41100024  /* Partial MMC_TXFIFO FIFO written */
+#define MMC_I_MASK	0x41100028  /* Interrupt Mask */
+#define MMC_I_REG	0x4110002c  /* Interrupt Register (read only) */
+#define MMC_CMD		0x41100030  /* Index of current command */
+#define MMC_ARGH	0x41100034  /* MSW part of the current command argument */
+#define MMC_ARGL	0x41100038  /* LSW part of the current command argument */
+#define MMC_RES		0x4110003c  /* Response FIFO (read only) */
+#define MMC_RXFIFO	0x41100040  /* Receive FIFO (read only) */
+#define MMC_TXFIFO	0x41100044  /* Transmit FIFO (write only) */
 
-#endif /* CONFIG_CPU_MONAHANS */
 
 /*
  * LCD
  */
-#define LCCR0		__REG(0x44000000)  /* LCD Controller Control Register 0 */
-#define LCCR1		__REG(0x44000004)  /* LCD Controller Control Register 1 */
-#define LCCR2		__REG(0x44000008)  /* LCD Controller Control Register 2 */
-#define LCCR3		__REG(0x4400000C)  /* LCD Controller Control Register 3 */
-#define DFBR0		__REG(0x44000020)  /* DMA Channel 0 Frame Branch Register */
-#define DFBR1		__REG(0x44000024)  /* DMA Channel 1 Frame Branch Register */
-#define LCSR0		__REG(0x44000038)  /* LCD Controller Status Register */
-#define LCSR1		__REG(0x44000034)  /* LCD Controller Status Register */
-#define LIIDR		__REG(0x4400003C)  /* LCD Controller Interrupt ID Register */
-#define TMEDRGBR	__REG(0x44000040)  /* TMED RGB Seed Register */
-#define TMEDCR		__REG(0x44000044)  /* TMED Control Register */
-
-#define FDADR0		__REG(0x44000200)  /* DMA Channel 0 Frame Descriptor Address Register */
-#define FSADR0		__REG(0x44000204)  /* DMA Channel 0 Frame Source Address Register */
-#define FIDR0		__REG(0x44000208)  /* DMA Channel 0 Frame ID Register */
-#define LDCMD0		__REG(0x4400020C)  /* DMA Channel 0 Command Register */
-#define FDADR1		__REG(0x44000210)  /* DMA Channel 1 Frame Descriptor Address Register */
-#define FSADR1		__REG(0x44000214)  /* DMA Channel 1 Frame Source Address Register */
-#define FIDR1		__REG(0x44000218)  /* DMA Channel 1 Frame ID Register */
-#define LDCMD1		__REG(0x4400021C)  /* DMA Channel 1 Command Register */
+#define LCCR0		0x44000000  /* LCD Controller Control Register 0 */
+#define LCCR1		0x44000004  /* LCD Controller Control Register 1 */
+#define LCCR2		0x44000008  /* LCD Controller Control Register 2 */
+#define LCCR3		0x4400000C  /* LCD Controller Control Register 3 */
+#define DFBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
+#define DFBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
+#define LCSR0		0x44000038  /* LCD Controller Status Register */
+#define LCSR1		0x44000034  /* LCD Controller Status Register */
+#define LIIDR		0x4400003C  /* LCD Controller Interrupt ID Register */
+#define TMEDRGBR	0x44000040  /* TMED RGB Seed Register */
+#define TMEDCR		0x44000044  /* TMED Control Register */
+
+#define FDADR0		0x44000200  /* DMA Channel 0 Frame Descriptor Address Register */
+#define FSADR0		0x44000204  /* DMA Channel 0 Frame Source Address Register */
+#define FIDR0		0x44000208  /* DMA Channel 0 Frame ID Register */
+#define LDCMD0		0x4400020C  /* DMA Channel 0 Command Register */
+#define FDADR1		0x44000210  /* DMA Channel 1 Frame Descriptor Address Register */
+#define FSADR1		0x44000214  /* DMA Channel 1 Frame Source Address Register */
+#define FIDR1		0x44000218  /* DMA Channel 1 Frame ID Register */
+#define LDCMD1		0x4400021C  /* DMA Channel 1 Command Register */
 
 #define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
 #define LCCR0_CMS	(1 << 1)	/* Color = 0, Monochrome = 1 */
@@ -2135,22 +2340,12 @@ typedef void		(*ExcpHndlr) (void) ;
 					/*  [0..255 Tln]		   */ \
 			((Tln) << FShft (LCCR2_BFW))
 
-#if 0
-#define LCCR3_PCD	(0xff)		/* Pixel clock divisor */
-#define LCCR3_ACB	(0xff << 8)	/* AC Bias pin frequency */
-#define LCCR3_ACB_S	8
-#endif
-
 #define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
 #define LCCR3_API_S	16
 #define LCCR3_VSP	(1 << 20)	/* vertical sync polarity */
 #define LCCR3_HSP	(1 << 21)	/* horizontal sync polarity */
 #define LCCR3_PCP	(1 << 22)	/* pixel clock polarity */
 #define LCCR3_OEP	(1 << 23)	/* output enable polarity */
-#if 0
-#define LCCR3_BPP	(7 << 24)	/* bits per pixel */
-#define LCCR3_BPP_S	24
-#endif
 #define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
 
 #define LCCR3_PDFOR_0	 (0 << 30)
@@ -2231,46 +2426,49 @@ typedef void		(*ExcpHndlr) (void) ;
  */
 
 #ifdef CONFIG_CPU_MONAHANS
+
+/* PXA3xx */
+
 /* Static Memory Controller Registers */
-#define MSC0		__REG_2(0x4A000008)  /* Static Memory Control Register 0 */
-#define MSC1		__REG_2(0x4A00000C)  /* Static Memory Control Register 1 */
-#define MECR		__REG_2(0x4A000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXCNFG		__REG_2(0x4A00001C)  /* Synchronous Static Memory Control Register */
-#define MCMEM0		__REG_2(0x4A000028)  /* Card interface Common Memory Space Socket 0 Timing */
-#define MCATT0		__REG_2(0x4A000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCIO0		__REG_2(0x4A000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MEMCLKCFG	__REG_2(0x4A000068)  /* SCLK speed configuration */
-#define CSADRCFG0	__REG_2(0x4A000080)  /* Address Configuration for chip select 0 */
-#define CSADRCFG1	__REG_2(0x4A000084)  /* Address Configuration for chip select 1 */
-#define CSADRCFG2	__REG_2(0x4A000088)  /* Address Configuration for chip select 2 */
-#define CSADRCFG3	__REG_2(0x4A00008C)  /* Address Configuration for chip select 3 */
-#define CSADRCFG_P	__REG_2(0x4A000090)  /* Address Configuration for pcmcia card interface */
-#define CSMSADRCFG	__REG_2(0x4A0000A0)  /* Master Address Configuration Register */
-#define CLK_RET_DEL	__REG_2(0x4A0000B0)  /* Delay line and mux selects for return data latching for sync. flash */
-#define ADV_RET_DEL	__REG_2(0x4A0000B4)  /* Delay line and mux selects for return data latching for sync. flash */
+#define	MSC0		0x4A000008 /* Static Memory Control Register 0 */
+#define	MSC1		0x4A00000C /* Static Memory Control Register 1 */
+#define	MECR		0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define	SXCNFG		0x4A00001C /* Synchronous Static Memory Control Register */
+#define	MCMEM0		0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */
+#define	MCATT0		0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define	MCIO0		0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */
+#define	MEMCLKCFG	0x4A000068 /* SCLK speed configuration */
+#define	CSADRCFG0	0x4A000080 /* Address Configuration for chip select 0 */
+#define	CSADRCFG1	0x4A000084 /* Address Configuration for chip select 1 */
+#define	CSADRCFG2	0x4A000088 /* Address Configuration for chip select 2 */
+#define	CSADRCFG3	0x4A00008C /* Address Configuration for chip select 3 */
+#define	CSADRCFG_P	0x4A000090 /* Address Configuration for pcmcia card interface */
+#define	CSMSADRCFG	0x4A0000A0 /* Master Address Configuration Register */
+#define	CLK_RET_DEL	0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */
+#define	ADV_RET_DEL	0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */
 
 /* Dynamic Memory Controller Registers */
-#define MDCNFG		__REG_2(0x48100000)  /* SDRAM Configuration Register 0 */
-#define MDREFR		__REG_2(0x48100004)  /* SDRAM Refresh Control Register */
-#define FLYCNFG		__REG_2(0x48100020)  /* Fly-by DMA DVAL[1:0] polarities */
-#define MDMRS		__REG_2(0x48100040)  /* MRS value to be written to SDRAM */
-#define	DDR_SCAL	__REG_2(0x48100050)  /* Software Delay Line Calibration/Configuration for external DDR memory. */
-#define	DDR_HCAL	__REG_2(0x48100060)  /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
-#define	DDR_WCAL	__REG_2(0x48100068)  /* DDR Write Strobe Calibration Register */
-#define	DMCIER		__REG_2(0x48100070)  /* Dynamic MC Interrupt Enable Register. */
-#define	DMCISR		__REG_2(0x48100078)  /* Dynamic MC Interrupt Status Register. */
-#define	DDR_DLS		__REG_2(0x48100080)  /* DDR Delay Line Value Status register for external DDR memory. */
-#define	EMPI		__REG_2(0x48100090)  /* EMPI Control Register */
-#define RCOMP           __REG_2(0x48100100)
-#define PAD_MA          __REG_2(0x48100110)
-#define PAD_MDMSB       __REG_2(0x48100114)
-#define PAD_MDLSB       __REG_2(0x48100118)
-#define PAD_DMEM        __REG_2(0x4810011c)
-#define PAD_SDCLK       __REG_2(0x48100120)
-#define PAD_SDCS        __REG_2(0x48100124)
-#define PAD_SMEM        __REG_2(0x48100128)
-#define PAD_SCLK        __REG_2(0x4810012C)
-#define TAI		__REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
+#define	MDCNFG		0x48100000 /* SDRAM Configuration Register 0 */
+#define	MDREFR		0x48100004 /* SDRAM Refresh Control Register */
+#define	FLYCNFG		0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
+#define	MDMRS		0x48100040 /* MRS value to be written to SDRAM */
+#define	DDR_SCAL	0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */
+#define	DDR_HCAL	0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
+#define	DDR_WCAL	0x48100068 /* DDR Write Strobe Calibration Register */
+#define	DMCIER		0x48100070 /* Dynamic MC Interrupt Enable Register. */
+#define	DMCISR		0x48100078 /* Dynamic MC Interrupt Status Register. */
+#define	DDR_DLS		0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */
+#define	EMPI		0x48100090 /* EMPI Control Register */
+#define	RCOMP		0x48100100
+#define	PAD_MA		0x48100110
+#define	PAD_MDMSB	0x48100114
+#define	PAD_MDLSB	0x48100118
+#define	PAD_DMEM	0x4810011c
+#define	PAD_SDCLK	0x48100120
+#define	PAD_SDCS	0x48100124
+#define	PAD_SMEM	0x48100128
+#define	PAD_SCLK	0x4810012C
+#define	TAI		0x48100F00 /* TAI Tavor Address Isolation Register */
 
 /* Some frequently used bits */
 #define MDCNFG_DMAP	0x80000000	/* SDRAM 1GB Memory Map Enable */
@@ -2298,19 +2496,19 @@ typedef void		(*ExcpHndlr) (void) ;
 
 /* Data Flash Controller Registers */
 
-#define NDCR		__REG(0x43100000)  /* Data Flash Control register */
-#define NDTR0CS0	__REG(0x43100004)  /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
-/* #define NDTR0CS1	__REG(0x43100008)  /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
-#define NDTR1CS0	__REG(0x4310000C)  /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
-/* #define NDTR1CS1	__REG(0x43100010)  /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
-#define NDSR		__REG(0x43100014)  /* Data Controller Status Register */
-#define NDPCR		__REG(0x43100018)  /* Data Controller Page Count Register */
-#define NDBDR0		__REG(0x4310001C)  /* Data Controller Bad Block Register 0 */
-#define NDBDR1		__REG(0x43100020)  /* Data Controller Bad Block Register 1 */
-#define NDDB		__REG(0x43100040)  /* Data Controller Data Buffer */
-#define NDCB0		__REG(0x43100048)  /* Data Controller Command Buffer0 */
-#define NDCB1		__REG(0x4310004C)  /* Data Controller Command Buffer1 */
-#define NDCB2		__REG(0x43100050)  /* Data Controller Command Buffer2 */
+#define NDCR		0x43100000  /* Data Flash Control register */
+#define NDTR0CS0	0x43100004  /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1	0x43100008  /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0	0x4310000C  /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1	0x43100010  /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR		0x43100014  /* Data Controller Status Register */
+#define NDPCR		0x43100018  /* Data Controller Page Count Register */
+#define NDBDR0		0x4310001C  /* Data Controller Bad Block Register 0 */
+#define NDBDR1		0x43100020  /* Data Controller Bad Block Register 1 */
+#define NDDB		0x43100040  /* Data Controller Data Buffer */
+#define NDCB0		0x43100048  /* Data Controller Command Buffer0 */
+#define NDCB1		0x4310004C  /* Data Controller Command Buffer1 */
+#define NDCB2		0x43100050  /* Data Controller Command Buffer2 */
 
 #define NDCR_SPARE_EN	(0x1<<31)
 #define NDCR_ECC_EN	(0x1<<30)
@@ -2386,7 +2584,9 @@ typedef void		(*ExcpHndlr) (void) ;
 
 #else /* CONFIG_CPU_MONAHANS */
 
-#define MEMC_BASE	__REG(0x48000000)  /* Base of Memory Controller */
+/* PXA2xx */
+
+#define MEMC_BASE	0x48000000  /* Base of Memory Controller */
 #define MDCNFG_OFFSET	0x0
 #define MDREFR_OFFSET	0x4
 #define MSC0_OFFSET	0x8
@@ -2405,29 +2605,30 @@ typedef void		(*ExcpHndlr) (void) ;
 #define MCIO1_OFFSET	0x3C
 #define MDMRS_OFFSET	0x40
 
-#define MDCNFG		__REG(0x48000000)  /* SDRAM Configuration Register 0 */
+#define MDCNFG		0x48000000  /* SDRAM Configuration Register 0 */
 #define MDCNFG_DE0	0x00000001
 #define MDCNFG_DE1	0x00000002
 #define MDCNFG_DE2	0x00010000
 #define MDCNFG_DE3	0x00020000
 #define MDCNFG_DWID0	0x00000004
 
-#define MDREFR		__REG(0x48000004)  /* SDRAM Refresh Control Register */
-#define MSC0		__REG(0x48000008)  /* Static Memory Control Register 0 */
-#define MSC1		__REG(0x4800000C)  /* Static Memory Control Register 1 */
-#define MSC2		__REG(0x48000010)  /* Static Memory Control Register 2 */
-#define MECR		__REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR		__REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG		__REG(0x4800001C)  /* Synchronous Static Memory Control Register */
-#define SXMRS		__REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0		__REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1		__REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0		__REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1		__REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0		__REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1		__REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS		__REG(0x48000040)  /* MRS value to be written to SDRAM */
-#define BOOT_DEF	__REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+#define MDREFR		0x48000004  /* SDRAM Refresh Control Register */
+#define MSC0		0x48000008  /* Static Memory Control Register 0 */
+#define MSC1		0x4800000C  /* Static Memory Control Register 1 */
+#define MSC2		0x48000010  /* Static Memory Control Register 2 */
+#define MECR		0x48000014  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR		0x48000018  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG		0x4800001C  /* Synchronous Static Memory Control Register */
+#define FLYCNFG		0x48000020
+#define SXMRS		0x48000024  /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0		0x48000028  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1		0x4800002C  /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0		0x48000030  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1		0x48000034  /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0		0x48000038  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1		0x4800003C  /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS		0x48000040  /* MRS value to be written to SDRAM */
+#define BOOT_DEF	0x48000044  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
 
 #define MDREFR_ALTREFA	(1 << 31)	/* Exiting Alternate Bus Master Mode Refresh Control */
 #define MDREFR_ALTREFB	(1 << 30)	/* Entering Alternate Bus Master Mode Refresh Control */
@@ -2448,7 +2649,7 @@ typedef void		(*ExcpHndlr) (void) ;
 
 #if defined(CONFIG_PXA27X)
 
-#define ARB_CNTRL	__REG(0x48000048)  /* Arbiter Control Register */
+#define ARB_CNTRL	0x48000048  /* Arbiter Control Register */
 
 #define ARB_DMA_SLV_PARK	(1<<31)	   /* Be parked with DMA slave when idle */
 #define ARB_CI_PARK		(1<<30)	   /* Be parked with Camera Interface when idle */
@@ -2460,80 +2661,41 @@ typedef void		(*ExcpHndlr) (void) ;
 #define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
 #define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
 
-#endif /* CONFIG_CPU_MONAHANS */
-
-/* Interrupt Controller */
-
-#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
-#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
-#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
-
-/* General Purpose I/O */
-
-#define GAFR3_L		__REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
-#define GAFR3_U		__REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
-#define GPLR3		__REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
-#define GPDR3		__REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
-#define GPSR3		__REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
-#define GPCR3		__REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO <127:96> */
-#define GRER3		__REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
-#define GFER3		__REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
-#define GEDR3		__REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
-
-/* Core Clock */
-
-#define CCSR		__REG(0x4130000C) /* Core Clock Status Register */
-
-#define CKEN23_SSP1	(1 << 23) /* SSP1 Unit Clock Enable */
-#define CKEN22_MEMC	(1 << 22) /* Memory Controler */
-#define CKEN21_MSHC	(1 << 21) /* Memery Stick Host Controller */
-#define CKEN20_IM	(1 << 20) /* Internal Memory Clock Enable */
-#define CKEN19_KEYPAD	(1 << 19) /* Keypad Interface Clock Enable */
-#define CKEN18_USIM	(1 << 18) /* USIM Unit Clock Enable */
-#define CKEN17_MSL	(1 << 17) /* MSL Interface Unit Clock Enable */
-#define CKEN15_PWR_I2C	(1 << 15) /* PWR_I2C Unit Clock Enable */
-#define CKEN9_OST	(1 << 9)  /* OS Timer Unit Clock Enable */
-#define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
-
-/* Memory controller */
-
-#define MDREFR_K0DB4	(1 << 29)	  /* SDCLK[0] divide by 4 */
+#endif /* CONFIG_PXA27X */
 
 /* LCD registers */
-#define LCCR4		__REG(0x44000010)  /* LCD Controller Control Register 4 */
-#define LCCR5		__REG(0x44000014)  /* LCD Controller Control Register 5 */
-#define FBR0		__REG(0x44000020)  /* DMA Channel 0 Frame Branch Register */
-#define FBR1		__REG(0x44000024)  /* DMA Channel 1 Frame Branch Register */
-#define FBR2		__REG(0x44000028)  /* DMA Channel 2 Frame Branch Register */
-#define FBR3		__REG(0x4400002C)  /* DMA Channel 3 Frame Branch Register */
-#define FBR4		__REG(0x44000030)  /* DMA Channel 4 Frame Branch Register */
-#define FDADR2		__REG(0x44000220)  /* DMA Channel 2 Frame Descriptor Address Register */
-#define FSADR2		__REG(0x44000224)  /* DMA Channel 2 Frame Source Address Register */
-#define FIDR2		__REG(0x44000228)  /* DMA Channel 2 Frame ID Register */
-#define LDCMD2		__REG(0x4400022C)  /* DMA Channel 2 Command Register */
-#define FDADR3		__REG(0x44000230)  /* DMA Channel 3 Frame Descriptor Address Register */
-#define FSADR3		__REG(0x44000234)  /* DMA Channel 3 Frame Source Address Register */
-#define FIDR3		__REG(0x44000238)  /* DMA Channel 3 Frame ID Register */
-#define LDCMD3		__REG(0x4400023C)  /* DMA Channel 3 Command Register */
-#define FDADR4		__REG(0x44000240)  /* DMA Channel 4 Frame Descriptor Address Register */
-#define FSADR4		__REG(0x44000244)  /* DMA Channel 4 Frame Source Address Register */
-#define FIDR4		__REG(0x44000248)  /* DMA Channel 4 Frame ID Register */
-#define LDCMD4		__REG(0x4400024C)  /* DMA Channel 4 Command Register */
-#define FDADR5		__REG(0x44000250)  /* DMA Channel 5 Frame Descriptor Address Register */
-#define FSADR5		__REG(0x44000254)  /* DMA Channel 5 Frame Source Address Register */
-#define FIDR5		__REG(0x44000258)  /* DMA Channel 5 Frame ID Register */
-#define LDCMD5		__REG(0x4400025C)  /* DMA Channel 5 Command Register */
-
-#define OVL1C1		__REG(0x44000050)  /* Overlay 1 Control Register 1 */
-#define OVL1C2		__REG(0x44000060)  /* Overlay 1 Control Register 2 */
-#define OVL2C1		__REG(0x44000070)  /* Overlay 2 Control Register 1 */
-#define OVL2C2		__REG(0x44000080)  /* Overlay 2 Control Register 2 */
-#define CCR		__REG(0x44000090)  /* Cursor Control Register */
-
-#define FBR5		__REG(0x44000110)  /* DMA Channel 5 Frame Branch Register */
-#define FBR6		__REG(0x44000114)  /* DMA Channel 6 Frame Branch Register */
+#define LCCR4		0x44000010  /* LCD Controller Control Register 4 */
+#define LCCR5		0x44000014  /* LCD Controller Control Register 5 */
+#define FBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
+#define FBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
+#define FBR2		0x44000028  /* DMA Channel 2 Frame Branch Register */
+#define FBR3		0x4400002C  /* DMA Channel 3 Frame Branch Register */
+#define FBR4		0x44000030  /* DMA Channel 4 Frame Branch Register */
+#define FDADR2		0x44000220  /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2		0x44000224  /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2		0x44000228  /* DMA Channel 2 Frame ID Register */
+#define LDCMD2		0x4400022C  /* DMA Channel 2 Command Register */
+#define FDADR3		0x44000230  /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3		0x44000234  /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3		0x44000238  /* DMA Channel 3 Frame ID Register */
+#define LDCMD3		0x4400023C  /* DMA Channel 3 Command Register */
+#define FDADR4		0x44000240  /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4		0x44000244  /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4		0x44000248  /* DMA Channel 4 Frame ID Register */
+#define LDCMD4		0x4400024C  /* DMA Channel 4 Command Register */
+#define FDADR5		0x44000250  /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5		0x44000254  /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5		0x44000258  /* DMA Channel 5 Frame ID Register */
+#define LDCMD5		0x4400025C  /* DMA Channel 5 Command Register */
+
+#define OVL1C1		0x44000050  /* Overlay 1 Control Register 1 */
+#define OVL1C2		0x44000060  /* Overlay 1 Control Register 2 */
+#define OVL2C1		0x44000070  /* Overlay 2 Control Register 1 */
+#define OVL2C2		0x44000080  /* Overlay 2 Control Register 2 */
+#define CCR		0x44000090  /* Cursor Control Register */
+
+#define FBR5		0x44000110  /* DMA Channel 5 Frame Branch Register */
+#define FBR6		0x44000114  /* DMA Channel 6 Frame Branch Register */
 
 #define LCCR0_LDDALT	(1<<26)		/* LDD Alternate mapping bit when base pixel is RGBT16 */
 #define LCCR0_OUC	(1<<25)		/* Overlay Underlay Control Bit */
@@ -2572,16 +2734,16 @@ typedef void		(*ExcpHndlr) (void) ;
 
 /* Keypad controller */
 
-#define KPC		__REG(0x41500000) /* Keypad Interface Control register */
-#define KPDK		__REG(0x41500008) /* Keypad Interface Direct Key register */
-#define KPREC		__REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */
-#define KPMK		__REG(0x41500018) /* Keypad Intefcace Matrix Key register */
-#define KPAS		__REG(0x41500020) /* Keypad Interface Automatic Scan register */
-#define KPASMKP0	__REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
-#define KPASMKP1	__REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
-#define KPASMKP2	__REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
-#define KPASMKP3	__REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
-#define KPKDI		__REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
+#define KPC		0x41500000 /* Keypad Interface Control register */
+#define KPDK		0x41500008 /* Keypad Interface Direct Key register */
+#define KPREC		0x41500010 /* Keypad Intefcace Rotary Encoder register */
+#define KPMK		0x41500018 /* Keypad Intefcace Matrix Key register */
+#define KPAS		0x41500020 /* Keypad Interface Automatic Scan register */
+#define KPASMKP0	0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
+#define KPASMKP1	0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
+#define KPASMKP2	0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
+#define KPASMKP3	0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
+#define KPKDI		0x41500048 /* Keypad Interface Key Debounce Interval register */
 
 #define KPC_AS		(0x1 << 30)  /* Automatic Scan bit */
 #define KPC_ASACT	(0x1 << 29)  /* Automatic Scan on Activity */
@@ -2623,15 +2785,15 @@ typedef void		(*ExcpHndlr) (void) ;
 #define KPASMKPx_SO	(0x1 << 31)
 
 #define GPIO113_BIT	(1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
-#define PSLR		__REG(0x40F00034)
-#define PSTR		__REG(0x40F00038)  /* Power Manager Standby Configuration Reg */
-#define PSNR		__REG(0x40F0003C)  /* Power Manager Sense Configuration Reg */
-#define PVCR		__REG(0x40F00040)  /* Power Manager Voltage Change Control Reg */
-#define PKWR		__REG(0x40F00050)  /* Power Manager KB Wake-Up Enable Reg */
-#define PKSR		__REG(0x40F00054)  /* Power Manager KB Level-Detect Status Reg */
-#define OSMR4		__REG(0x40A00080)  /* */
-#define OSCR4		__REG(0x40A00040)  /* OS Timer Counter Register */
-#define OMCR4		__REG(0x40A000C0)  /* */
+#define PSLR		0x40F00034
+#define PSTR		0x40F00038  /* Power Manager Standby Configuration Reg */
+#define PSNR		0x40F0003C  /* Power Manager Sense Configuration Reg */
+#define PVCR		0x40F00040  /* Power Manager Voltage Change Control Reg */
+#define PKWR		0x40F00050  /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR		0x40F00054  /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4		0x40A00080  /* */
+#define OSCR4		0x40A00040  /* OS Timer Counter Register */
+#define OMCR4		0x40A000C0  /* */
 
 #endif	/* CONFIG_PXA27X */
 
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 4e8dfd7..4124f0a 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -21,8 +21,9 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* Relocation to SDRAM works on all ARM boards */
 #define CONFIG_RELOC_FIXUP_WORKS
-#endif
+
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 6152f34..6dae432 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -47,6 +47,20 @@ typedef	struct	global_data {
 #ifdef CONFIG_FSL_ESDHC
 	unsigned long	sdhc_clk;
 #endif
+#ifdef CONFIG_AT91FAMILY
+	/* "static data" needed by at91's clock.c */
+	unsigned long	cpu_clk_rate_hz;
+	unsigned long	main_clk_rate_hz;
+	unsigned long	mck_rate_hz;
+	unsigned long	plla_rate_hz;
+	unsigned long	pllb_rate_hz;
+	unsigned long	at91_pllb_usb_init;
+	/* "static data" needed by at91's timer.c */
+	unsigned long	timer_rate_hz;
+	unsigned long	tbl;
+	unsigned long	tbu;
+	unsigned long long	timer_reset_value;
+#endif
 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
 	phys_size_t	ram_size;	/* RAM size */
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index faf800a..4ac4f61 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -30,18 +30,18 @@
 #define _U_BOOT_ARM_H_	1
 
 /* for the following variables, see start.S */
-extern ulong _bss_start;	/* code + data end == BSS start */
-extern ulong _bss_end;		/* BSS end */
+extern ulong _bss_start_ofs;	/* BSS start relative to _start */
+extern ulong _bss_end_ofs;		/* BSS end relative to _start */
 extern ulong IRQ_STACK_START;	/* top of IRQ stack */
 extern ulong FIQ_STACK_START;	/* top of FIQ stack */
 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-extern ulong _armboot_start;	/* code start */
+extern ulong _armboot_start_ofs;	/* code start */
 #else
 extern ulong _TEXT_BASE;	/* code start */
-extern ulong _datarel_start;
-extern ulong _datarelrolocal_start;
-extern ulong _datarellocal_start;
-extern ulong _datarelro_start;
+extern ulong _datarel_start_ofs;
+extern ulong _datarelrolocal_start_ofs;
+extern ulong _datarellocal_start_ofs;
+extern ulong _datarelro_start_ofs;
 extern ulong IRQ_STACK_START_IN;	/* 8 bytes in IRQ stack */
 #endif
 
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 108e6c4..ffe261b 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -147,7 +147,7 @@ static int display_banner (void)
 #else
 	       _armboot_start,
 #endif
-	       _bss_start, _bss_end);
+	       _bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE);
 #ifdef CONFIG_MODEM_SUPPORT
 	debug ("Modem Support enabled\n");
 #endif
@@ -508,7 +508,7 @@ void board_init_f (ulong bootflag)
 
 	memset ((void*)gd, 0, sizeof (gd_t));
 
-	gd->mon_len = _bss_end - _TEXT_BASE;
+	gd->mon_len = _bss_end_ofs;
 
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
 		if ((*init_fnc_ptr)() != 0) {
@@ -670,6 +670,7 @@ static char *failed = "*** failed ***\n";
  *
  ************************************************************************
  */
+
 void board_init_r (gd_t *id, ulong dest_addr)
 {
 	char *s;
@@ -693,7 +694,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
-	monitor_flash_len = _bss_start - _TEXT_BASE;
+	monitor_flash_len = _bss_start_ofs;
 	debug ("monitor flash len: %08lX\n", monitor_flash_len);
 	board_init();	/* Setup chipselects */
 
@@ -895,6 +896,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	/* NOTREACHED - no way out of command loop except booting */
 }
+
 #endif /* defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 
 void hang (void)
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 3101321..2e7b2e1 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -26,6 +26,9 @@
 #include <image.h>
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
+#include <fdt.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,12 +53,52 @@ static void setup_end_tag (bd_t *bd);
 static struct tag *params;
 #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
 
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
+static ulong get_sp(void);
+#if defined(CONFIG_OF_LIBFDT)
+static int bootm_linux_fdt(int machid, bootm_headers_t *images);
+#endif
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+	ulong sp;
+
+	/*
+	 * Booting a (Linux) kernel image
+	 *
+	 * Allocate space for command line and board info - the
+	 * address should be as high as possible within the reach of
+	 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+	 * memory, which means far enough below the current stack
+	 * pointer.
+	 */
+	sp = get_sp();
+	debug("## Current stack ends at 0x%08lx ", sp);
+
+	/* adjust sp by 1K to be safe */
+	sp -= 1024;
+	lmb_reserve(lmb, sp,
+		    gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
+}
+
+static void announce_and_cleanup(void)
+{
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+	cleanup_before_linux();
+}
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 {
 	bd_t	*bd = gd->bd;
 	char	*s;
 	int	machid = bd->bi_arch_number;
-	void	(*theKernel)(int zero, int arch, uint params);
+	void	(*kernel_entry)(int zero, int arch, uint params);
 
 #ifdef CONFIG_CMDLINE_TAG
 	char *commandline = getenv ("bootargs");
@@ -64,8 +107,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
 		return 1;
 
-	theKernel = (void (*)(int, int, uint))images->ep;
-
 	s = getenv ("machid");
 	if (s) {
 		machid = simple_strtoul (s, NULL, 16);
@@ -74,8 +115,15 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 
 	show_boot_progress (15);
 
+#ifdef CONFIG_OF_LIBFDT
+	if (images->ft_len)
+		return bootm_linux_fdt(machid, images);
+#endif
+
+	kernel_entry = (void (*)(int, int, uint))images->ep;
+
 	debug ("## Transferring control to Linux (at address %08lx) ...\n",
-	       (ulong) theKernel);
+	       (ulong) kernel_entry);
 
 #if defined (CONFIG_SETUP_MEMORY_TAGS) || \
     defined (CONFIG_CMDLINE_TAG) || \
@@ -99,27 +147,76 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 	if (images->rd_start && images->rd_end)
 		setup_initrd_tag (bd, images->rd_start, images->rd_end);
 #endif
-	setup_end_tag (bd);
+	setup_end_tag(bd);
 #endif
 
-	/* we assume that the kernel is in place */
-	printf ("\nStarting kernel ...\n\n");
+	announce_and_cleanup();
 
-#ifdef CONFIG_USB_DEVICE
-	{
-		extern void udc_disconnect (void);
-		udc_disconnect ();
+	kernel_entry(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+static int fixup_memory_node(void *blob)
+{
+	bd_t	*bd = gd->bd;
+	int bank;
+	u64 start[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start[bank] = bd->bi_dram[bank].start;
+		size[bank] = bd->bi_dram[bank].size;
 	}
-#endif
 
-	cleanup_before_linux ();
+	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
+
+static int bootm_linux_fdt(int machid, bootm_headers_t *images)
+{
+	ulong rd_len;
+	bd_t *bd = gd->bd;
+	char *s;
+	void (*kernel_entry)(int zero, int dt_machid, void *dtblob);
+	ulong bootmap_base = getenv_bootm_low();
+	ulong of_size = images->ft_len;
+	char **of_flat_tree = &images->ft_addr;
+	ulong *initrd_start = &images->initrd_start;
+	ulong *initrd_end = &images->initrd_end;
+	struct lmb *lmb = &images->lmb;
+	int ret;
+
+	kernel_entry = (void (*)(int, int, void *))images->ep;
+
+	rd_len = images->rd_end - images->rd_start;
+	ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
+				initrd_start, initrd_end);
+	if (ret)
+		return ret;
+
+	ret = boot_relocate_fdt(lmb, bootmap_base, of_flat_tree, &of_size);
+	if (ret)
+		return ret;
 
-	theKernel (0, machid, bd->bi_boot_params);
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong) kernel_entry);
+
+	fdt_chosen(*of_flat_tree, 1);
+
+	fixup_memory_node(*of_flat_tree);
+
+	fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+
+	announce_and_cleanup();
+
+	kernel_entry(0, machid, *of_flat_tree);
 	/* does not return */
 
 	return 1;
 }
-
+#endif
 
 #if defined (CONFIG_SETUP_MEMORY_TAGS) || \
     defined (CONFIG_CMDLINE_TAG) || \
@@ -239,4 +336,12 @@ static void setup_end_tag (bd_t *bd)
 	params->hdr.size = 0;
 }
 
+static ulong get_sp(void)
+{
+	ulong ret;
+
+	asm("mov %0, sp" : "=r"(ret) : );
+	return ret;
+}
+
 #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 55b633e..5715168 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -38,7 +38,7 @@ void  flush_cache (unsigned long dummy1, unsigned long dummy2)
 	/* disable write buffer as well (page 2-22) */
 	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 #endif
-#ifdef CONFIG_ARMCORTEXA8
+#ifdef CONFIG_ARMV7
 	void v7_flush_cache_all(void);
 
 	v7_flush_cache_all();
diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h
index 36438be..ec2cc16 100644
--- a/arch/m68k/include/asm/config.h
+++ b/arch/m68k/include/asm/config.h
@@ -22,5 +22,8 @@
 #define _ASM_CONFIG_H_
 
 #define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define CONFIG_SYS_BOOT_GET_CMDLINE
+#define CONFIG_SYS_BOOT_GET_KBD
 
 #endif
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 8e2c6d8..9f6d6d6 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -46,12 +46,9 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 
 	char	*of_flat_tree = NULL;
 #if defined(CONFIG_OF_LIBFDT)
-	ulong	of_size = 0;
-
-	/* find flattened device tree */
-	ret = boot_get_fdt (flag, argc, argv, images, &of_flat_tree, &of_size);
-	if (ret)
-		return 1;
+	/* did generic code already find a device tree? */
+	if (images->ft_len)
+		of_flat_tree = images->ft_addr;
 #endif
 
 	theKernel = (void (*)(char *, ulong, ulong))images->ep;
@@ -64,9 +61,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 
 	show_boot_progress (15);
 
-	if (!(ulong) of_flat_tree)
-		of_flat_tree = (char *)simple_strtoul (argv[3], NULL, 16);
-
+	if (!of_flat_tree && argc > 3)
+		of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
 #ifdef DEBUG
 	printf ("## Transferring control to Linux (at address 0x%08lx) " \
 				"ramdisk 0x%08lx, FDT 0x%08lx...\n",
diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c
index 40a4d15..f32be52 100644
--- a/arch/nios2/lib/bootm.c
+++ b/arch/nios2/lib/bootm.c
@@ -36,11 +36,9 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 	ulong initrd_end = images->rd_end;
 	char *of_flat_tree = NULL;
 #if defined(CONFIG_OF_LIBFDT)
-	ulong of_size = 0;
-
-	/* find flattened device tree */
-	if (boot_get_fdt(flag, argc, argv, images, &of_flat_tree, &of_size))
-		return 1;
+	/* did generic code already find a device tree? */
+	if (images->ft_len)
+		of_flat_tree = images->ft_addr;
 #endif
 	if (!of_flat_tree && argc > 3)
 		of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index d098657..a1942ca 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -22,6 +22,9 @@
 #define _ASM_CONFIG_H_
 
 #define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define CONFIG_SYS_BOOT_GET_CMDLINE
+#define CONFIG_SYS_BOOT_GET_KBD
 
 #ifndef CONFIG_MAX_MEM_MAPPED
 #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
diff --git a/arch/sparc/include/asm/config.h b/arch/sparc/include/asm/config.h
index 36438be..6ddc349 100644
--- a/arch/sparc/include/asm/config.h
+++ b/arch/sparc/include/asm/config.h
@@ -22,5 +22,6 @@
 #define _ASM_CONFIG_H_
 
 #define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
 
 #endif