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authorJason Liu <r64343@freescale.com>2013-05-23 16:59:42 +0800
committerJason Liu <r64343@freescale.com>2013-05-24 09:28:12 +0800
commit4bd0032c0eba50fa0caf43f50f735a3cfbe36a8d (patch)
tree9e8bcb2c3c6c0117d0d0af6a7859037e56917e5b /arch
parent6f04955aa81e688087ed6cf73802f8acfe065fe5 (diff)
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ENGR00264076-5 i.mx6:shutdown vddpu and pcie phy to save power
shutdown vddpu and pcie phy to save power Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 2e84d89..7409df8 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -325,6 +325,34 @@ static void imx_reset_pfd(void)
#endif
}
+static void imx_set_vddpu_power_down(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ u32 val;
+
+ /* need to power down xPU in GPC before turn off PU LDO */
+ val = readl(GPC_BASE_ADDR + 0x260);
+ writel(val | 0x1, GPC_BASE_ADDR + 0x260);
+
+ val = readl(GPC_BASE_ADDR + 0x0);
+ writel(val | 0x1, GPC_BASE_ADDR + 0x0);
+ while (readl(GPC_BASE_ADDR + 0x0) & 0x1)
+ ;
+
+ /* disable VDDPU */
+ val = 0x3e00;
+ writel(val, &anatop->reg_core_clr);
+}
+
+static void imx_set_pcie_phy_power_down(void)
+{
+ u32 val;
+
+ val = readl(IOMUXC_BASE_ADDR + 0x4);
+ val |= 0x1 << 18;
+ writel(val, IOMUXC_BASE_ADDR + 0x4);
+}
+
int arch_cpu_init(void)
{
init_aips();
@@ -333,6 +361,8 @@ int arch_cpu_init(void)
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
imx_reset_pfd();
+ imx_set_pcie_phy_power_down();
+ imx_set_vddpu_power_down();
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */