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| author | Nishanth Menon <nm@ti.com> | 2012-03-01 14:17:39 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 08:31:22 +0200 |
| commit | f2ae6c1a83e194dfd0fc93348efe598353f3c02d (patch) | |
| tree | 58a19b6094653ad1c26640feac041c8425892391 /arch | |
| parent | 3acb553439e3ee9f62f022f96f949c21811f8bdf (diff) | |
| download | u-boot-imx-f2ae6c1a83e194dfd0fc93348efe598353f3c02d.zip u-boot-imx-f2ae6c1a83e194dfd0fc93348efe598353f3c02d.tar.gz u-boot-imx-f2ae6c1a83e194dfd0fc93348efe598353f3c02d.tar.bz2 | |
OMAP4: scale voltage of core before MPU scales
OMAP4 requires that parent domains scale ahead of dependent domains.
This is due to the restrictions in timing closure. To ensure
a consistent behavior across all OMAP4 SoC, ensure that
vdd_core scale first, then vdd_mpu and finally vdd_iva.
As part of doing this refactor the logic to allow for future
addition of OMAP4470 without much ado. OMAP4470 uses different
SMPS addresses and cannot be introduced in the current code
without major rewrite.
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/clocks.c | 63 |
1 files changed, 35 insertions, 28 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 1431312..b6b3f7e 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -278,44 +278,51 @@ void scale_vcores(void) omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); omap_rev = omap_revision(); - /* TPS - supplies vdd_mpu on 4460 */ - if (omap_rev >= OMAP4460_ES1_0) { - volt = 1203; - do_scale_tps62361(TPS62361_VSEL0_GPIO, - TPS62361_REG_ADDR_SET1, volt); - } /* - * VCORE 1 - * - * 4430 : supplies vdd_mpu - * Setting a high voltage for Nitro mode as smart reflex is not enabled. - * We use the maximum possible value in the AVS range because the next - * higher voltage in the discrete range (code >= 0b111010) is way too - * high - * - * 4460 : supplies vdd_core + * Scale Voltage rails: + * 1. VDD_CORE + * 3. VDD_MPU + * 3. VDD_IVA */ if (omap_rev < OMAP4460_ES1_0) { + /* + * OMAP4430: + * VDD_CORE = TWL6030 VCORE3 + * VDD_MPU = TWL6030 VCORE1 + * VDD_IVA = TWL6030 VCORE2 + */ + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); + + /* + * note on VDD_MPU: + * Setting a high voltage for Nitro mode as smart reflex is not + * enabled. We use the maximum possible value in the AVS range + * because the next higher voltage in the discrete range + * (code >= 0b111010) is way too high. + */ volt = 1325; do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); + } else { + /* + * OMAP4460: + * VDD_CORE = TWL6030 VCORE1 + * VDD_MPU = TPS62361 + * VDD_IVA = TWL6030 VCORE2 + */ volt = 1200; do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); - } - - /* VCORE 2 - supplies vdd_iva */ - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); - - /* - * VCORE 3 - * 4430 : supplies vdd_core - * 4460 : not connected - */ - if (omap_rev < OMAP4460_ES1_0) { + /* TPS62361 */ + volt = 1203; + do_scale_tps62361(TPS62361_VSEL0_GPIO, + TPS62361_REG_ADDR_SET1, volt); + /* VCORE 2 - supplies vdd_iva */ volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); + do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); } } |