diff options
| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2012-08-14 08:43:07 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-15 11:54:14 -0700 |
| commit | 9e0081d573442e7234355f0a043218d15df03933 (patch) | |
| tree | bc508d9fa9b248d70cac2ed736d834d22f5e0e3b /arch | |
| parent | b809b3ac13e1016b2be937bd4511973f90982ad2 (diff) | |
| download | u-boot-imx-9e0081d573442e7234355f0a043218d15df03933.zip u-boot-imx-9e0081d573442e7234355f0a043218d15df03933.tar.gz u-boot-imx-9e0081d573442e7234355f0a043218d15df03933.tar.bz2 | |
mx31: Fix PDR0_CSI_PODF
The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0
register is actually composed of two bit-fields: one pre-divider and one
post-divider. This patch fixes the CCM access macros and the code using them
accordingly.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-mx31/imx-regs.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index c3919be..8fd3d08 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -569,7 +569,8 @@ struct esdc_regs { #define MX31_IIM_BASE_ADDR 0x5001C000 -#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) +#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26) +#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23) #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) @@ -592,7 +593,8 @@ struct esdc_regs { #define PLL_MFI(x) (((x) & 0xf) << 10) #define PLL_MFN(x) (((x) & 0x3ff) << 0) -#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff) +#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f) +#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7) #define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) #define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) #define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) |