Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
	drivers/video/exynos_fb.c

15 files changed, 174 insertions, 1458 deletions

diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c
index ff52131..9f0c1d1 100644
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ b/arch/arm/cpu/arm926ejs/spear/spear600.c
@@ -28,9 +28,6 @@
 #include <asm/arch/spr_misc.h>
 #include <asm/arch/spr_defs.h>
 
-#define FALSE				0
-#define TRUE				(!FALSE)
-
 static void sel_1v8(void)
 {
 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@@ -133,8 +130,8 @@ void soc_init(void)
 /*
  * xxx_boot_selected:
  *
- * return TRUE if the particular booting option is selected
- * return FALSE otherwise
+ * return true if the particular booting option is selected
+ * return false otherwise
  */
 static u32 read_bootstrap(void)
 {
@@ -150,18 +147,18 @@ int snor_boot_selected(void)
 		/* Check whether SNOR boot is selected */
 		if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
 			CONFIG_SPEAR_ONLYSNORBOOT)
-			return TRUE;
+			return true;
 
 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND8BOOT)
-			return TRUE;
+			return true;
 
 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND16BOOT)
-			return TRUE;
+			return true;
 	}
 
-	return FALSE;
+	return false;
 }
 
 int nand_boot_selected(void)
@@ -172,20 +169,20 @@ int nand_boot_selected(void)
 		/* Check whether NAND boot is selected */
 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND8BOOT)
-			return TRUE;
+			return true;
 
 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND16BOOT)
-			return TRUE;
+			return true;
 	}
 
-	return FALSE;
+	return false;
 }
 
 int pnor_boot_selected(void)
 {
 	/* Parallel NOR boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int usb_boot_selected(void)
@@ -195,39 +192,39 @@ int usb_boot_selected(void)
 	if (USB_BOOT_SUPPORTED) {
 		/* Check whether USB boot is selected */
 		if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
-			return TRUE;
+			return true;
 	}
 
-	return FALSE;
+	return false;
 }
 
 int tftp_boot_selected(void)
 {
 	/* TFTP boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int uart_boot_selected(void)
 {
 	/* UART boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int spi_boot_selected(void)
 {
 	/* SPI boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int i2c_boot_selected(void)
 {
 	/* I2C boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int mmc_boot_selected(void)
 {
-	return FALSE;
+	return false;
 }
 
 void plat_late_init(void)
diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
index f2f9a49..3e2953c 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
@@ -120,7 +120,7 @@ u32 spl_boot(void)
 	/*
 	 * All the supported booting devices are listed here. Each of
 	 * the booting type supported by the platform would define the
-	 * macro xxx_BOOT_SUPPORTED to TRUE.
+	 * macro xxx_BOOT_SUPPORTED to true.
 	 */
 
 	if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
index e088832..9f63c34 100644
--- a/arch/arm/cpu/pxa/Makefile
+++ b/arch/arm/cpu/pxa/Makefile
@@ -33,7 +33,6 @@ COBJS-$(CONFIG_CPU_PXA27X)	= pxa2xx.o
 COBJS-y	+= cpuinfo.o
 
 COBJS	= $(COBJS-y)
-COBJS	+= pxafb.o
 COBJS	+= timer.o
 COBJS	+= usb.o
 
diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
deleted file mode 100644
index 987fa06..0000000
--- a/arch/arm/cpu/pxa/pxafb.c
+++ /dev/null
@@ -1,652 +0,0 @@
-/*
- * PXA LCD Controller
- *
- * (C) Copyright 2001-2002
- * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************/
-/* ** HEADER FILES							*/
-/************************************************************************/
-
-#include <config.h>
-#include <common.h>
-#include <version.h>
-#include <stdarg.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-#include <lcd.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-/* #define DEBUG */
-
-#ifdef CONFIG_LCD
-
-/*----------------------------------------------------------------------*/
-/*
- * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
- * your display.
- */
-
-#ifdef CONFIG_PXA_VGA
-/* LCD outputs connected to a video DAC  */
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f8
-# define REG_LCCR3	0x0300FF01
-
-/* 640x480x16 @ 61 Hz */
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 640,
-	.vl_height	= 480,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 0,
-	.vl_clor	= 0,
-	.vl_tft		= 1,
-	.vl_hpw		= 40,
-	.vl_blw		= 56,
-	.vl_elw		= 56,
-	.vl_vpw		= 20,
-	.vl_bfw		= 8,
-	.vl_efw		= 8,
-};
-#endif /* CONFIG_PXA_VIDEO */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_SHARP_LM8V31
-
-# define LCD_BPP	LCD_COLOR8
-# define LCD_INVERT_COLORS	/* Needed for colors to be correct, but why?	*/
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x0030087C
-# define REG_LCCR3	0x0340FF08
-
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 157,
-	.vl_height	= 118,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 0,
-	.vl_hpw		= 1,
-	.vl_blw		= 3,
-	.vl_elw		= 3,
-	.vl_vpw		= 1,
-	.vl_bfw		= 0,
-	.vl_efw		= 0,
-};
-#endif /* CONFIG_SHARP_LM8V31 */
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_VOIPAC_LCD
-
-# define LCD_BPP	LCD_COLOR8
-# define LCD_INVERT_COLORS
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x043008f8
-# define REG_LCCR3	0x0340FF08
-
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 157,
-	.vl_height	= 118,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 32,
-	.vl_blw		= 144,
-	.vl_elw		= 32,
-	.vl_vpw		= 2,
-	.vl_bfw		= 13,
-	.vl_efw		= 30,
-};
-#endif /* CONFIG_VOIPAC_LCD */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_HITACHI_SX14
-/* Hitachi SX14Q004-ZZA color STN LCD */
-#define LCD_BPP		LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-#define REG_LCCR0	0x00301079
-#define REG_LCCR3	0x0340FF20
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 240,
-	.vl_width	= 167,
-	.vl_height	= 109,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 1,
-	.vl_splt	= 0,
-	.vl_clor	= 1,
-	.vl_tft		= 0,
-	.vl_hpw		= 1,
-	.vl_blw		= 1,
-	.vl_elw		= 1,
-	.vl_vpw		= 7,
-	.vl_bfw		= 0,
-	.vl_efw		= 0,
-};
-#endif /* CONFIG_HITACHI_SX14 */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_LMS283GF05
-
-# define LCD_BPP	LCD_COLOR8
-/*# define LCD_INVERT_COLORS*/
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x043008f8
-# define REG_LCCR3	0x03b00009
-
-vidinfo_t panel_info = {
-	.vl_col		= 240,
-	.vl_row		= 320,
-	.vl_width	= 240,
-	.vl_height	= 320,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 4,
-	.vl_blw		= 4,
-	.vl_elw		= 8,
-	.vl_vpw		= 4,
-	.vl_bfw		= 4,
-	.vl_efw		= 8,
-};
-#endif /* CONFIG_LMS283GF05 */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_ACX517AKN
-
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f9
-# define REG_LCCR3	0x03700006
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 320,
-	.vl_width	= 320,
-	.vl_height	= 320,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 0x04,
-	.vl_blw		= 0x1c,
-	.vl_elw		= 0x08,
-	.vl_vpw		= 0x01,
-	.vl_bfw		= 0x07,
-	.vl_efw		= 0x08,
-};
-#endif /* CONFIG_ACX517AKN */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_LQ038J7DH53
-
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f9
-# define REG_LCCR3	0x03700004
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 480,
-	.vl_width	= 320,
-	.vl_height	= 480,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 0x04,
-	.vl_blw		= 0x20,
-	.vl_elw		= 0x01,
-	.vl_vpw		= 0x01,
-	.vl_bfw		= 0x04,
-	.vl_efw		= 0x01,
-};
-#endif /* CONFIG_ACX517AKN */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_LITTLETON_LCD
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f8
-# define REG_LCCR3	0x0300FF04
-
-vidinfo_t panel_info = {
-	.vl_col		= 480,
-	.vl_row		= 640,
-	.vl_width	= 480,
-	.vl_height	= 640,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 0,
-	.vl_clor	= 0,
-	.vl_tft		= 1,
-	.vl_hpw		= 9,
-	.vl_blw		= 8,
-	.vl_elw		= 24,
-	.vl_vpw		= 2,
-	.vl_bfw		= 2,
-	.vl_efw		= 4,
-};
-#endif /* CONFIG_LITTLETON_LCD */
-
-/*----------------------------------------------------------------------*/
-
-#if LCD_BPP == LCD_COLOR8
-void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
-#endif
-#if LCD_BPP == LCD_MONOCHROME
-void lcd_initcolregs (void);
-#endif
-
-#ifdef NOT_USED_SO_FAR
-void lcd_disable (void);
-void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
-#endif /* NOT_USED_SO_FAR */
-
-void lcd_ctrl_init	(void *lcdbase);
-void lcd_enable	(void);
-
-int lcd_line_length;
-int lcd_color_fg;
-int lcd_color_bg;
-
-void *lcd_base;			/* Start of framebuffer memory	*/
-void *lcd_console_address;		/* Start of console buffer	*/
-
-short console_col;
-short console_row;
-
-static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
-static void pxafb_setup_gpio (vidinfo_t *vid);
-static void pxafb_enable_controller (vidinfo_t *vid);
-static int pxafb_init (vidinfo_t *vid);
-/************************************************************************/
-
-/************************************************************************/
-/* ---------------  PXA chipset specific functions  ------------------- */
-/************************************************************************/
-
-void lcd_ctrl_init (void *lcdbase)
-{
-	pxafb_init_mem(lcdbase, &panel_info);
-	pxafb_init(&panel_info);
-	pxafb_setup_gpio(&panel_info);
-	pxafb_enable_controller(&panel_info);
-}
-
-/*----------------------------------------------------------------------*/
-#ifdef NOT_USED_SO_FAR
-void
-lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
-{
-}
-#endif /* NOT_USED_SO_FAR */
-
-/*----------------------------------------------------------------------*/
-#if LCD_BPP == LCD_COLOR8
-void
-lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
-{
-	struct pxafb_info *fbi = &panel_info.pxa;
-	unsigned short *palette = (unsigned short *)fbi->palette;
-	u_int val;
-
-	if (regno < fbi->palette_size) {
-		val = ((red << 8) & 0xf800);
-		val |= ((green << 4) & 0x07e0);
-		val |= (blue & 0x001f);
-
-#ifdef LCD_INVERT_COLORS
-		palette[regno] = ~val;
-#else
-		palette[regno] = val;
-#endif
-	}
-
-	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
-		regno, &palette[regno],
-		red, green, blue,
-		palette[regno]);
-}
-#endif /* LCD_COLOR8 */
-
-/*----------------------------------------------------------------------*/
-#if LCD_BPP == LCD_MONOCHROME
-void lcd_initcolregs (void)
-{
-	struct pxafb_info *fbi = &panel_info.pxa;
-	cmap = (ushort *)fbi->palette;
-	ushort regno;
-
-	for (regno = 0; regno < 16; regno++) {
-		cmap[regno * 2] = 0;
-		cmap[(regno * 2) + 1] = regno & 0x0f;
-	}
-}
-#endif /* LCD_MONOCHROME */
-
-/*----------------------------------------------------------------------*/
-void lcd_enable (void)
-{
-}
-
-/*----------------------------------------------------------------------*/
-#ifdef	NOT_USED_SO_FAR
-static void lcd_disable (void)
-{
-}
-#endif /* NOT_USED_SO_FAR */
-
-/*----------------------------------------------------------------------*/
-
-/************************************************************************/
-/* ** PXA255 specific routines						*/
-/************************************************************************/
-
-/*
- * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
- * descriptors and palette areas.
- */
-ulong calc_fbsize (void)
-{
-	ulong size;
-	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
-
-	size = line_length * panel_info.vl_row;
-	size += PAGE_SIZE;
-
-	return size;
-}
-
-static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
-{
-	u_long palette_mem_size;
-	struct pxafb_info *fbi = &vid->pxa;
-	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
-
-	fbi->screen = (u_long)lcdbase;
-
-	fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
-	palette_mem_size = fbi->palette_size * sizeof(u16);
-
-	debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
-	/* locate palette and descs at end of page following fb */
-	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
-
-	return 0;
-}
-#ifdef	CONFIG_CPU_MONAHANS
-static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
-#else
-static void pxafb_setup_gpio (vidinfo_t *vid)
-{
-	u_long lccr0;
-
-	/*
-	 * setup is based on type of panel supported
-	 */
-
-	lccr0 = vid->pxa.reg_lccr0;
-
-	/* 4 bit interface */
-	if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
-	{
-		debug("Setting GPIO for 4 bit data\n");
-		/* bits 58-61 */
-		writel(readl(GPDR1) | (0xf << 26), GPDR1);
-		writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR1_U);
-
-		/* bits 74-77 */
-		writel(readl(GPDR2) | (0xf << 10), GPDR2);
-		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR2_L);
-	}
-
-	/* 8 bit interface */
-	else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
-		(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
-	{
-		debug("Setting GPIO for 8 bit data\n");
-		/* bits 58-65 */
-		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
-		writel(readl(GPDR2) | (0x3), GPDR2);
-
-		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
-			GAFR1_U);
-		writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
-
-		/* bits 74-77 */
-		writel(readl(GPDR2) | (0xf << 10), GPDR2);
-		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR2_L);
-	}
-
-	/* 16 bit interface */
-	else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
-	{
-		debug("Setting GPIO for 16 bit data\n");
-		/* bits 58-77 */
-		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
-		writel(readl(GPDR2) | 0x00003fff, GPDR2);
-
-		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
-			GAFR1_U);
-		writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
-	}
-	else
-	{
-		printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
-	}
-}
-#endif
-
-static void pxafb_enable_controller (vidinfo_t *vid)
-{
-	debug("Enabling LCD controller\n");
-
-	/* Sequence from 11.7.10 */
-	writel(vid->pxa.reg_lccr3, LCCR3);
-	writel(vid->pxa.reg_lccr2, LCCR2);
-	writel(vid->pxa.reg_lccr1, LCCR1);
-	writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
-	writel(vid->pxa.fdadr0, FDADR0);
-	writel(vid->pxa.fdadr1, FDADR1);
-	writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
-
-#ifdef	CONFIG_CPU_MONAHANS
-	writel(readl(CKENA) | CKENA_1_LCD, CKENA);
-#else
-	writel(readl(CKEN) | CKEN16_LCD, CKEN);
-#endif
-
-	debug("FDADR0 = 0x%08x\n", readl(FDADR0));
-	debug("FDADR1 = 0x%08x\n", readl(FDADR1));
-	debug("LCCR0 = 0x%08x\n", readl(LCCR0));
-	debug("LCCR1 = 0x%08x\n", readl(LCCR1));
-	debug("LCCR2 = 0x%08x\n", readl(LCCR2));
-	debug("LCCR3 = 0x%08x\n", readl(LCCR3));
-}
-
-static int pxafb_init (vidinfo_t *vid)
-{
-	struct pxafb_info *fbi = &vid->pxa;
-
-	debug("Configuring PXA LCD\n");
-
-	fbi->reg_lccr0 = REG_LCCR0;
-	fbi->reg_lccr3 = REG_LCCR3;
-
-	debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
-		vid->vl_col, vid->vl_hpw,
-		vid->vl_blw, vid->vl_elw);
-	debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
-		vid->vl_row, vid->vl_vpw,
-		vid->vl_bfw, vid->vl_efw);
-
-	fbi->reg_lccr1 =
-		LCCR1_DisWdth(vid->vl_col) +
-		LCCR1_HorSnchWdth(vid->vl_hpw) +
-		LCCR1_BegLnDel(vid->vl_blw) +
-		LCCR1_EndLnDel(vid->vl_elw);
-
-	fbi->reg_lccr2 =
-		LCCR2_DisHght(vid->vl_row) +
-		LCCR2_VrtSnchWdth(vid->vl_vpw) +
-		LCCR2_BegFrmDel(vid->vl_bfw) +
-		LCCR2_EndFrmDel(vid->vl_efw);
-
-	fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
-	fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
-			| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
-
-
-	/* setup dma descriptors */
-	fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
-	fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
-	fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
-
-	#define BYTES_PER_PANEL	((fbi->reg_lccr0 & LCCR0_SDS) ? \
-		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
-		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
-
-	/* populate descriptors */
-	fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
-	fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
-	fbi->dmadesc_fblow->fidr  = 0;
-	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
-
-	fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
-
-	fbi->dmadesc_fbhigh->fsadr = fbi->screen;
-	fbi->dmadesc_fbhigh->fidr = 0;
-	fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
-
-	fbi->dmadesc_palette->fsadr = fbi->palette;
-	fbi->dmadesc_palette->fidr  = 0;
-	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
-
-	if( NBITS(vid->vl_bpix) < 12)
-	{
-		/* assume any mode with <12 bpp is palette driven */
-		fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
-		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
-		/* flips back and forth between pal and fbhigh */
-		fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
-	}
-	else
-	{
-		/* palette shouldn't be loaded in true-color mode */
-		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
-		fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
-	}
-
-	debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
-	debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
-	debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
-
-	debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
-	debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
-	debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
-
-	debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
-	debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
-	debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
-
-	debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
-	debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
-	debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
-
-	return 0;
-}
-
-/************************************************************************/
-/************************************************************************/
-
-#endif /* CONFIG_LCD */
diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h
index 000ffe5..1f28b36 100644
--- a/arch/blackfin/include/asm/posix_types.h
+++ b/arch/blackfin/include/asm/posix_types.h
@@ -61,9 +61,6 @@ typedef unsigned int __kernel_gid32_t;
 typedef unsigned short __kernel_old_uid_t;
 typedef unsigned short __kernel_old_gid_t;
 
-#define BOOL_WAS_DEFINED
-typedef enum { false = 0, true = 1 } bool;
-
 #ifdef __GNUC__
 typedef long long __kernel_loff_t;
 #endif
diff --git a/arch/m68k/lib/interrupts.c b/arch/m68k/lib/interrupts.c
index 133494f..9751db4 100644
--- a/arch/m68k/lib/interrupts.c
+++ b/arch/m68k/lib/interrupts.c
@@ -96,7 +96,7 @@ int disable_interrupts (void)
 	sr = get_sr ();
 	set_sr (sr | 0x0700);
 
-	return ((sr & 0x0700) == 0);	/* return TRUE, if interrupts were enabled before */
+	return ((sr & 0x0700) == 0);	/* return true, if interrupts were enabled before */
 }
 
 void int_handler (struct pt_regs *fp)
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
index ca8c227..b4d0adc 100644
--- a/arch/nds32/lib/interrupts.c
+++ b/arch/nds32/lib/interrupts.c
@@ -59,7 +59,7 @@ void enable_interrupts(void)
 
 /*
  * disable interrupts
- * Return TRUE if GIE is enabled before we disable it.
+ * Return true if GIE is enabled before we disable it.
  */
 int disable_interrupts(void)
 {
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 5495dc5..825a292 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -513,7 +513,7 @@ void fsl_serdes_init(void)
 	size_t arglen;
 #endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
-	int need_serdes_a001;	/* TRUE == need work-around for SERDES A001 */
+	int need_serdes_a001;	/* true == need work-around for SERDES A001 */
 #endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 	char buffer[HWCONFIG_BUFFER_SIZE];
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
index 0d1a12c..ef10e2d 100644
--- a/arch/powerpc/cpu/mpc8xx/Makefile
+++ b/arch/powerpc/cpu/mpc8xx/Makefile
@@ -37,7 +37,6 @@ COBJS-y	+= fec.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-y	+= i2c.o
 COBJS-y	+= interrupts.o
-COBJS-y	+= lcd.o
 COBJS-y	+= scc.o
 COBJS-y	+= serial.o
 COBJS-y	+= speed.o
diff --git a/arch/powerpc/cpu/mpc8xx/lcd.c b/arch/powerpc/cpu/mpc8xx/lcd.c
deleted file mode 100644
index 4b88b21..0000000
--- a/arch/powerpc/cpu/mpc8xx/lcd.c
+++ /dev/null
@@ -1,621 +0,0 @@
-/*
- * (C) Copyright 2001-2002
- * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************/
-/* ** HEADER FILES							*/
-/************************************************************************/
-
-/* #define DEBUG */
-
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include <watchdog.h>
-#include <version.h>
-#include <stdarg.h>
-#include <lcdvideo.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-#if defined(CONFIG_POST)
-#include <post.h>
-#endif
-#include <lcd.h>
-
-#ifdef CONFIG_LCD
-
-/************************************************************************/
-/* ** CONFIG STUFF -- should be moved to board config file		*/
-/************************************************************************/
-#ifndef CONFIG_LCD_INFO
-#define CONFIG_LCD_INFO		/* Display Logo, (C) and system info	*/
-#endif
-
-#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
-#undef CONFIG_LCD_LOGO
-#undef CONFIG_LCD_INFO
-#endif
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_KYOCERA_KCS057QV1AJ
-/*
- *  Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
- */
-#define LCD_BPP	LCD_COLOR4
-
-vidinfo_t panel_info = {
-    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
-    LCD_BPP, 1, 0, 1, 0,  5, 0, 0, 0
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_KYOCERA_KCS057QV1AJ */
-/*----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_HITACHI_SP19X001_Z1A
-/*
- *  Hitachi SP19X001-. Active, color, single scan.
- */
-vidinfo_t panel_info = {
-    640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
-    LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_HITACHI_SP19X001_Z1A */
-/*----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_NEC_NL6448AC33
-/*
- *  NEC NL6448AC33-18. Active, color, single scan.
- */
-vidinfo_t panel_info = {
-    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
-    3, 0, 0, 1, 1, 144, 2, 0, 33
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_NEC_NL6448AC33 */
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_NEC_NL6448BC20
-/*
- *  NEC NL6448BC20-08.  6.5", 640x480. Active, color, single scan.
- */
-vidinfo_t panel_info = {
-    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
-    3, 0, 0, 1, 1, 144, 2, 0, 33
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_NEC_NL6448BC20 */
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_NEC_NL6448BC33_54
-/*
- *  NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
- */
-vidinfo_t panel_info = {
-    640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
-    3, 0, 0, 1, 1, 144, 2, 0, 33
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_NEC_NL6448BC33_54 */
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_SHARP_LQ104V7DS01
-/*
- *  SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
- */
-vidinfo_t panel_info = {
-    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
-    3, 0, 0, 1, 1, 25, 1, 0, 33
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_SHARP_LQ104V7DS01 */
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_SHARP_16x9
-/*
- * Sharp 320x240. Active, color, single scan.  It isn't 16x9, and I am
- * not sure what it is.......
- */
-vidinfo_t panel_info = {
-    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
-    3, 0, 0, 1, 1, 15, 4, 0, 3
-};
-#endif /* CONFIG_SHARP_16x9 */
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_SHARP_LQ057Q3DC02
-/*
- * Sharp LQ057Q3DC02 display. Active, color, single scan.
- */
-#undef LCD_DF
-#define LCD_DF 12
-
-vidinfo_t panel_info = {
-    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
-    3, 0, 0, 1, 1, 15, 4, 0, 3
-		/* wbl, vpw, lcdac, wbf */
-};
-#define CONFIG_LCD_INFO_BELOW_LOGO
-#endif /* CONFIG_SHARP_LQ057Q3DC02 */
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_SHARP_LQ64D341
-/*
- * Sharp LQ64D341 display, 640x480. Active, color, single scan.
- */
-vidinfo_t panel_info = {
-    640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
-    3, 0, 0, 1, 1, 128, 16, 0, 32
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_SHARP_LQ64D341 */
-
-#ifdef CONFIG_SHARP_LQ065T9DR51U
-/*
- * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
- */
-vidinfo_t panel_info = {
-    400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
-    3, 0, 0, 1, 1, 248, 4, 0, 35
-		/* wbl, vpw, lcdac, wbf */
-};
-#define CONFIG_LCD_INFO_BELOW_LOGO
-#endif /* CONFIG_SHARP_LQ065T9DR51U */
-
-#ifdef CONFIG_SHARP_LQ084V1DG21
-/*
- * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
- */
-vidinfo_t panel_info = {
-    640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
-    3, 0, 0, 1, 1, 160, 3, 0, 48
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_SHARP_LQ084V1DG21 */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_HLD1045
-/*
- * HLD1045 display, 640x480. Active, color, single scan.
- */
-vidinfo_t panel_info = {
-    640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
-    3, 0, 0, 1, 1, 160, 3, 0, 48
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_HLD1045 */
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_PRIMEVIEW_V16C6448AC
-/*
- * Prime View V16C6448AC
- */
-vidinfo_t panel_info = {
-    640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
-    3, 0, 0, 1, 1, 144, 2, 0, 35
-		/* wbl, vpw, lcdac, wbf */
-};
-#endif /* CONFIG_PRIMEVIEW_V16C6448AC */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_OPTREX_BW
-/*
- * Optrex   CBL50840-2 NF-FW 99 22 M5
- * or
- * Hitachi  LMG6912RPFC-00T
- * or
- * Hitachi  SP14Q002
- *
- * 320x240. Black & white.
- */
-#define OPTREX_BPP	0	/* 0 - monochrome,     1 bpp */
-				/* 1 -  4 grey levels, 2 bpp */
-				/* 2 - 16 grey levels, 4 bpp */
-vidinfo_t panel_info = {
-    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
-    OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
-};
-#endif /* CONFIG_OPTREX_BW */
-
-/*-----------------------------------------------------------------*/
-#ifdef CONFIG_EDT32F10
-/*
- * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
- */
-#define LCD_BPP		LCD_MONOCHROME
-#define LCD_DF		10
-
-vidinfo_t panel_info = {
-    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
-    LCD_BPP,  0, 0, 0, 0, 33, 0, 0, 0
-};
-#endif
-/*----------------------------------------------------------------------*/
-
-
-int lcd_line_length;
-
-int lcd_color_fg;
-int lcd_color_bg;
-
-/*
- * Frame buffer memory information
- */
-void *lcd_base;			/* Start of framebuffer memory	*/
-void *lcd_console_address;	/* Start of console buffer	*/
-
-short console_col;
-short console_row;
-
-/************************************************************************/
-
-void lcd_ctrl_init (void *lcdbase);
-void lcd_enable (void);
-#if LCD_BPP == LCD_COLOR8
-void lcd_setcolreg (ushort regno,
-				ushort red, ushort green, ushort blue);
-#endif
-#if LCD_BPP == LCD_MONOCHROME
-void lcd_initcolregs (void);
-#endif
-
-#if defined(CONFIG_RBC823)
-void lcd_disable (void);
-#endif
-
-/************************************************************************/
-
-/************************************************************************/
-/* ----------------- chipset specific functions ----------------------- */
-/************************************************************************/
-
-/*
- * Calculate fb size for VIDEOLFB_ATAG.
- */
-ulong calc_fbsize (void)
-{
-	ulong size;
-	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
-
-	size = line_length * panel_info.vl_row;
-
-	return size;
-}
-
-void lcd_ctrl_init (void *lcdbase)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile lcd823_t *lcdp = &immr->im_lcd;
-
-	uint lccrtmp;
-	uint lchcr_hpc_tmp;
-
-	/* Initialize the LCD control register according to the LCD
-	 * parameters defined.  We do everything here but enable
-	 * the controller.
-	 */
-
-#ifdef CONFIG_RPXLITE
-	/* This is special for RPXlite_DW Software Development Platform **[Sam]** */
-	panel_info.vl_dp = CONFIG_SYS_LOW;
-#endif
-
-	lccrtmp  = LCDBIT (LCCR_BNUM_BIT,
-		   (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
-
-	lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp)	|
-		   LCDBIT (LCCR_OEP_BIT,  panel_info.vl_oep)	|
-		   LCDBIT (LCCR_HSP_BIT,  panel_info.vl_hsp)	|
-		   LCDBIT (LCCR_VSP_BIT,  panel_info.vl_vsp)	|
-		   LCDBIT (LCCR_DP_BIT,   panel_info.vl_dp)	|
-		   LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix)	|
-		   LCDBIT (LCCR_LBW_BIT,  panel_info.vl_lbw)	|
-		   LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt)	|
-		   LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor)	|
-		   LCDBIT (LCCR_TFT_BIT,  panel_info.vl_tft);
-
-#if 0
-	lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
-	lccrtmp |= LCCR_EIEN;
-#endif
-
-	lcdp->lcd_lccr = lccrtmp;
-	lcdp->lcd_lcsr = 0xFF;		/* Clear pending interrupts */
-
-	/* Initialize LCD controller bus priorities.
-	 */
-#ifdef CONFIG_RBC823
-	immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1;	/* RAID = 01, LAID = 00 */
-#else
-	immr->im_siu_conf.sc_sdcr &= ~0x0f;	/* RAID = LAID = 0 */
-
-	/* set SHFT/CLOCK division factor 4
-	 * This needs to be set based upon display type and processor
-	 * speed.  The TFT displays run about 20 to 30 MHz.
-	 * I was running 64 MHz processor speed.
-	 * The value for this divider must be chosen so the result is
-	 * an integer of the processor speed (i.e., divide by 3 with
-	 * 64 MHz would be bad).
-	 */
-	immr->im_clkrst.car_sccr &= ~0x1F;
-	immr->im_clkrst.car_sccr |= LCD_DF;	/* was 8 */
-
-#endif /* CONFIG_RBC823 */
-
-#if defined(CONFIG_RBC823)
-	/* Enable LCD on port D.
-	 */
-	immr->im_ioport.iop_pddat &= 0x0300;
-	immr->im_ioport.iop_pdpar |= 0x1CFF;
-	immr->im_ioport.iop_pddir |= 0x1CFF;
-
-	/* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
-	 */
-	immr->im_cpm.cp_pbdat &= ~0x00005001;
-	immr->im_cpm.cp_pbpar &= ~0x00005001;
-	immr->im_cpm.cp_pbdir |=  0x00005001;
-#elif !defined(CONFIG_EDT32F10)
-	/* Enable LCD on port D.
-	 */
-	immr->im_ioport.iop_pdpar |= 0x1FFF;
-	immr->im_ioport.iop_pddir |= 0x1FFF;
-
-	/* Enable LCD_A/B/C on port B.
-	 */
-	immr->im_cpm.cp_pbpar |= 0x00005001;
-	immr->im_cpm.cp_pbdir |= 0x00005001;
-#else
-	/* Enable LCD on port D.
-	 */
-	immr->im_ioport.iop_pdpar |= 0x1DFF;
-	immr->im_ioport.iop_pdpar &= ~0x0200;
-	immr->im_ioport.iop_pddir |= 0x1FFF;
-	immr->im_ioport.iop_pddat |= 0x0200;
-#endif
-
-	/* Load the physical address of the linear frame buffer
-	 * into the LCD controller.
-	 * BIG NOTE:  This has to be modified to load A and B depending
-	 * upon the split mode of the LCD.
-	 */
-	lcdp->lcd_lcfaa = (ulong)lcd_base;
-	lcdp->lcd_lcfba = (ulong)lcd_base;
-
-	/* MORE HACKS...This must be updated according to 823 manual
-	 * for different panels.
-	 * Udi Finkelstein - done - see below:
-	 * Note: You better not try unsupported combinations such as
-	 * 4-bit wide passive dual scan LCD at 4/8 Bit color.
-	 */
-	lchcr_hpc_tmp =
-		(panel_info.vl_col *
-		 (panel_info.vl_tft ? 8 :
-			(((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
-			 /* use << to mult by: single scan = 1, dual scan = 2 */
-			  panel_info.vl_splt) *
-			 (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
-
-	lcdp->lcd_lchcr = LCHCR_BO |
-			  LCDBIT (LCHCR_AT_BIT, 4) |
-			  LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
-			  panel_info.vl_wbl;
-
-	lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
-			  LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
-			  LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
-			  panel_info.vl_wbf;
-
-}
-
-/*----------------------------------------------------------------------*/
-
-#ifdef	NOT_USED_SO_FAR
-static void
-lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile cpm8xx_t *cp = &(immr->im_cpm);
-	unsigned short colreg, *cmap_ptr;
-
-	cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
-
-	colreg = *cmap_ptr;
-#ifdef	CONFIG_SYS_INVERT_COLORS
-	colreg ^= 0x0FFF;
-#endif
-
-	*red   = (colreg >> 8) & 0x0F;
-	*green = (colreg >> 4) & 0x0F;
-	*blue  =  colreg       & 0x0F;
-}
-#endif	/* NOT_USED_SO_FAR */
-
-/*----------------------------------------------------------------------*/
-
-#if LCD_BPP == LCD_COLOR8
-void
-lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile cpm8xx_t *cp = &(immr->im_cpm);
-	unsigned short colreg, *cmap_ptr;
-
-	cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
-
-	colreg = ((red   & 0x0F) << 8) |
-		 ((green & 0x0F) << 4) |
-		  (blue  & 0x0F) ;
-#ifdef	CONFIG_SYS_INVERT_COLORS
-	colreg ^= 0x0FFF;
-#endif
-	*cmap_ptr = colreg;
-
-	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
-		regno, &(cp->lcd_cmap[regno * 2]),
-		red, green, blue,
-		cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
-}
-#endif	/* LCD_COLOR8 */
-
-/*----------------------------------------------------------------------*/
-
-#if LCD_BPP == LCD_MONOCHROME
-static
-void lcd_initcolregs (void)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile cpm8xx_t *cp = &(immr->im_cpm);
-	ushort regno;
-
-	for (regno = 0; regno < 16; regno++) {
-		cp->lcd_cmap[regno * 2] = 0;
-		cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
-	}
-}
-#endif
-
-/*----------------------------------------------------------------------*/
-
-void lcd_enable (void)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile lcd823_t *lcdp = &immr->im_lcd;
-
-	/* Enable the LCD panel */
-#ifndef CONFIG_RBC823
-	immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25));		/* LAM = 1 */
-#endif
-	lcdp->lcd_lccr |= LCCR_PON;
-
-#ifdef CONFIG_V37
-	/* Turn on display backlight */
-	immr->im_cpm.cp_pbpar |= 0x00008000;
-	immr->im_cpm.cp_pbdir |= 0x00008000;
-#elif defined(CONFIG_RBC823)
-	/* Turn on display backlight */
-	immr->im_cpm.cp_pbdat |= 0x00004000;
-#endif
-
-#if defined(CONFIG_LWMON)
-    {	uchar c = pic_read (0x60);
-#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
-	/* Enable LCD later in sysmon test, only if temperature is OK */
-#else
-	c |= 0x07;	/* Power on CCFL, Enable CCFL, Chip Enable LCD */
-#endif
-	pic_write (0x60, c);
-    }
-#endif /* CONFIG_LWMON */
-
-#if defined(CONFIG_R360MPI)
-    {
-	extern void r360_i2c_lcd_write (uchar data0, uchar data1);
-	unsigned long bgi, ctr;
-	char *p;
-
-	if ((p = getenv("lcdbgi")) != NULL) {
-		bgi = simple_strtoul (p, 0, 10) & 0xFFF;
-	} else {
-		bgi = 0xFFF;
-	}
-
-	if ((p = getenv("lcdctr")) != NULL) {
-		ctr = simple_strtoul (p, 0, 10) & 0xFFF;
-	} else {
-		ctr=0x7FF;
-	}
-
-	r360_i2c_lcd_write(0x10, 0x01);
-	r360_i2c_lcd_write(0x20, 0x01);
-	r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
-	r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
-    }
-#endif /* CONFIG_R360MPI */
-#ifdef CONFIG_RBC823
-	udelay(200000); /* wait 200ms */
-	/* Turn VEE_ON first */
-	immr->im_cpm.cp_pbdat |= 0x00000001;
-	udelay(200000); /* wait 200ms */
-	/* Now turn on LCD_ON */
-	immr->im_cpm.cp_pbdat |= 0x00001000;
-#endif
-#ifdef CONFIG_RRVISION
-	debug ("PC4->Output(1): enable LVDS\n");
-	debug ("PC5->Output(0): disable PAL clock\n");
-	immr->im_ioport.iop_pddir |=  0x1000;
-	immr->im_ioport.iop_pcpar &= ~(0x0C00);
-	immr->im_ioport.iop_pcdir |=   0x0C00 ;
-	immr->im_ioport.iop_pcdat |=   0x0800 ;
-	immr->im_ioport.iop_pcdat &= ~(0x0400);
-	debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
-	       immr->im_ioport.iop_pdpar,
-	       immr->im_ioport.iop_pddir,
-	       immr->im_ioport.iop_pddat);
-	debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
-	       immr->im_ioport.iop_pcpar,
-	       immr->im_ioport.iop_pcdir,
-	       immr->im_ioport.iop_pcdat);
-#endif
-}
-
-/*----------------------------------------------------------------------*/
-
-#if defined (CONFIG_RBC823)
-void lcd_disable (void)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile lcd823_t *lcdp = &immr->im_lcd;
-
-#if defined(CONFIG_LWMON)
-    {	uchar c = pic_read (0x60);
-	c &= ~0x07;	/* Power off CCFL, Disable CCFL, Chip Disable LCD */
-	pic_write (0x60, c);
-    }
-#elif defined(CONFIG_R360MPI)
-    {
-	extern void r360_i2c_lcd_write (uchar data0, uchar data1);
-
-	r360_i2c_lcd_write(0x10, 0x00);
-	r360_i2c_lcd_write(0x20, 0x00);
-	r360_i2c_lcd_write(0x30, 0x00);
-	r360_i2c_lcd_write(0x40, 0x00);
-    }
-#endif /* CONFIG_LWMON */
-	/* Disable the LCD panel */
-	lcdp->lcd_lccr &= ~LCCR_PON;
-#ifdef CONFIG_RBC823
-	/* Turn off display backlight, VEE and LCD_ON */
-	immr->im_cpm.cp_pbdat &= ~0x00005001;
-#else
-	immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25));	/* LAM = 0 */
-#endif /* CONFIG_RBC823 */
-}
-#endif	/* NOT_USED_SO_FAR || CONFIG_RBC823 */
-
-
-/************************************************************************/
-
-#endif /* CONFIG_LCD */
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 2847094..2db9045 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -167,6 +167,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 				}
 			}
 
+			if (mode_idx < 0 || phy_idx < 0) {
+				puts("ERROR: wrong usb mode/phy defined!!\n");
+				return;
+			}
+
 			dr_mode_type = modes[mode_idx];
 			dr_phy_type = phys[phy_idx];
 
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
index 8a20a2b..161d274 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
@@ -88,8 +88,6 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))
 #define NUMMEMTESTS		8
 #define NUMMEMWORDS		8
 #define MAXBXCR			4
-#define TRUE			1
-#define FALSE			0
 
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
@@ -298,7 +296,7 @@ static void get_spd_info(unsigned long *dimm_populated,
 	unsigned char num_of_bytes;
 	unsigned char total_size;
 
-	dimm_found = FALSE;
+	dimm_found = false;
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		num_of_bytes = 0;
 		total_size = 0;
@@ -307,16 +305,16 @@ static void get_spd_info(unsigned long *dimm_populated,
 		total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 
 		if ((num_of_bytes != 0) && (total_size != 0)) {
-			dimm_populated[dimm_num] = TRUE;
-			dimm_found = TRUE;
+			dimm_populated[dimm_num] = true;
+			dimm_found = true;
 			debug("DIMM slot %lu: populated\n", dimm_num);
 		} else {
-			dimm_populated[dimm_num] = FALSE;
+			dimm_populated[dimm_num] = false;
 			debug("DIMM slot %lu: Not populated\n", dimm_num);
 		}
 	}
 
-	if (dimm_found == FALSE) {
+	if (dimm_found == false) {
 		printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 		spd_ddr_init_hang ();
 	}
@@ -330,7 +328,7 @@ static void check_mem_type(unsigned long *dimm_populated,
 	unsigned char dimm_type;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 			switch (dimm_type) {
 			case 7:
@@ -356,7 +354,7 @@ static void check_volt_type(unsigned long *dimm_populated,
 	unsigned long voltage_type;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 			if (voltage_type != 0x04) {
 				printf("ERROR: DIMM %lu with unsupported voltage level.\n",
@@ -398,12 +396,12 @@ static void program_cfg0(unsigned long *dimm_populated,
 	/*
 	 * FIXME: assume the DDR SDRAMs in both banks are the same
 	 */
-	ecc_enabled = TRUE;
+	ecc_enabled = true;
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 			if (ecc != 0x02) {
-				ecc_enabled = FALSE;
+				ecc_enabled = false;
 			}
 
 			/*
@@ -437,7 +435,7 @@ static void program_cfg0(unsigned long *dimm_populated,
 	/*
 	 * program Memory Data Error Checking
 	 */
-	if (ecc_enabled == TRUE) {
+	if (ecc_enabled == true) {
 		cfg0 |= SDRAM_CFG0_MCHK_GEN;
 	} else {
 		cfg0 |= SDRAM_CFG0_MCHK_NON;
@@ -493,7 +491,7 @@ static void program_rtr(unsigned long *dimm_populated,
 	bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 
 	for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
 			switch (refresh_rate_type) {
 			case 0x00:
@@ -585,15 +583,15 @@ static void program_tr0(unsigned long *dimm_populated,
 	t_rp_ns = 0;
 	t_rcd_ns = 0;
 	t_ras_ns = 0;
-	cas_2_0_available = TRUE;
-	cas_2_5_available = TRUE;
-	cas_3_0_available = TRUE;
+	cas_2_0_available = true;
+	cas_2_5_available = true;
+	cas_3_0_available = true;
 	tcyc_2_0_ns_x_10 = 0;
 	tcyc_2_5_ns_x_10 = 0;
 	tcyc_3_0_ns_x_10 = 0;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
 			t_rp_ns	 = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
 			t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
@@ -640,7 +638,7 @@ static void program_tr0(unsigned long *dimm_populated,
 				if (cas_index != 0) {
 					cas_index++;
 				}
-				cas_3_0_available = FALSE;
+				cas_3_0_available = false;
 			}
 
 			if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
@@ -650,7 +648,7 @@ static void program_tr0(unsigned long *dimm_populated,
 				if (cas_index != 0) {
 					cas_index++;
 				}
-				cas_2_5_available = FALSE;
+				cas_2_5_available = false;
 			}
 
 			if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
@@ -660,7 +658,7 @@ static void program_tr0(unsigned long *dimm_populated,
 				if (cas_index != 0) {
 					cas_index++;
 				}
-				cas_2_0_available = FALSE;
+				cas_2_0_available = false;
 			}
 
 			break;
@@ -683,13 +681,13 @@ static void program_tr0(unsigned long *dimm_populated,
 	/*
 	 * Program SD_CASL field
 	 */
-	if ((cas_2_0_available == TRUE) &&
+	if ((cas_2_0_available == true) &&
 	    (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
 		tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
-	} else if ((cas_2_5_available == TRUE) &&
+	} else if ((cas_2_5_available == true) &&
 		 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
 		tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
-	} else if ((cas_3_0_available == TRUE) &&
+	} else if ((cas_3_0_available == true) &&
 		 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
 		tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
 	} else {
@@ -950,9 +948,9 @@ static void program_tr1(void)
 	current_fail_length = 0;
 	current_start = 0;
 	rdclt_offset = 0;
-	window_found = FALSE;
-	fail_found = FALSE;
-	pass_found = FALSE;
+	window_found = false;
+	fail_found = false;
+	pass_found = false;
 	debug("Starting memory test ");
 
 	for (k = 0; k < NUMHALFCYCLES; k++) {
@@ -963,8 +961,8 @@ static void program_tr1(void)
 			mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
 
 			if (short_mem_test()) {
-				if (fail_found == TRUE) {
-					pass_found = TRUE;
+				if (fail_found == true) {
+					pass_found = true;
 					if (current_pass_length == 0) {
 						current_start = rdclt_offset + rdclt;
 					}
@@ -983,10 +981,10 @@ static void program_tr1(void)
 				current_fail_length++;
 
 				if (current_fail_length >= (dly_val>>2)) {
-					if (fail_found == FALSE) {
-						fail_found = TRUE;
-					} else if (pass_found == TRUE) {
-						window_found = TRUE;
+					if (fail_found == false) {
+						fail_found = true;
+					} else if (pass_found == true) {
+						window_found = true;
 						break;
 					}
 				}
@@ -994,9 +992,8 @@ static void program_tr1(void)
 		}
 		debug(".");
 
-		if (window_found == TRUE) {
+		if (window_found == true)
 			break;
-		}
 
 		tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
 		rdclt_offset += dly_val;
@@ -1006,7 +1003,7 @@ static void program_tr1(void)
 	/*
 	 * make sure we find the window
 	 */
-	if (window_found == FALSE) {
+	if (window_found == false) {
 		printf("ERROR: Cannot determine a common read delay.\n");
 		spd_ddr_init_hang ();
 	}
@@ -1115,7 +1112,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
 	bank_base_addr = CONFIG_SYS_SDRAM_BASE;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
 			num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
 			num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 85217ea..def7ebf 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -241,13 +241,6 @@ void board_add_ram_info(int use_default)
 /*-----------------------------------------------------------------------------+
  * Defines
  *-----------------------------------------------------------------------------*/
-#ifndef	TRUE
-#define TRUE		1
-#endif
-#ifndef FALSE
-#define FALSE		0
-#endif
-
 #define SDRAM_DDR1	1
 #define SDRAM_DDR2	2
 #define SDRAM_NONE	0
@@ -683,7 +676,7 @@ static void get_spd_info(unsigned long *dimm_populated,
 	unsigned char num_of_bytes;
 	unsigned char total_size;
 
-	dimm_found = FALSE;
+	dimm_found = false;
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		num_of_bytes = 0;
 		total_size = 0;
@@ -696,16 +689,16 @@ static void get_spd_info(unsigned long *dimm_populated,
 		      iic0_dimm_addr[dimm_num], total_size);
 
 		if ((num_of_bytes != 0) && (total_size != 0)) {
-			dimm_populated[dimm_num] = TRUE;
-			dimm_found = TRUE;
+			dimm_populated[dimm_num] = true;
+			dimm_found = true;
 			debug("DIMM slot %lu: populated\n", dimm_num);
 		} else {
-			dimm_populated[dimm_num] = FALSE;
+			dimm_populated[dimm_num] = false;
 			debug("DIMM slot %lu: Not populated\n", dimm_num);
 		}
 	}
 
-	if (dimm_found == FALSE) {
+	if (dimm_found == false) {
 		printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 		spd_ddr_init_hang ();
 	}
@@ -724,7 +717,7 @@ static void check_mem_type(unsigned long *dimm_populated,
 	unsigned long dimm_type;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 			switch (dimm_type) {
 			case 1:
@@ -994,14 +987,14 @@ static void program_copt1(unsigned long *dimm_populated,
 	unsigned long val;
 
 #ifdef CONFIG_DDR_ECC
-	ecc_enabled = TRUE;
+	ecc_enabled = true;
 #else
-	ecc_enabled = FALSE;
+	ecc_enabled = false;
 #endif
-	dimm_32bit = FALSE;
-	dimm_64bit = FALSE;
-	buf0 = FALSE;
-	buf1 = FALSE;
+	dimm_32bit = false;
+	dimm_64bit = false;
+	buf0 = false;
+	buf1 = false;
 
 	/*------------------------------------------------------------------
 	 * Set memory controller options reg 1, SDRAM_MCOPT1.
@@ -1026,7 +1019,7 @@ static void program_copt1(unsigned long *dimm_populated,
 			/* test ecc support */
 			ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 			if (ecc != 0x02) /* ecc not supported */
-				ecc_enabled = FALSE;
+				ecc_enabled = false;
 
 			/* test bank count */
 			bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
@@ -1048,15 +1041,15 @@ static void program_copt1(unsigned long *dimm_populated,
 				if (registered == 1) { /* DDR2 always buffered */
 					/* TODO: what about above  comments ? */
 					mcopt1 |= SDRAM_MCOPT1_RDEN;
-					buf0 = TRUE;
+					buf0 = true;
 				} else {
 					/* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
 					if ((attribute & 0x02) == 0x00) {
 						/* buffered not supported */
-						buf0 = FALSE;
+						buf0 = false;
 					} else {
 						mcopt1 |= SDRAM_MCOPT1_RDEN;
-						buf0 = TRUE;
+						buf0 = true;
 					}
 				}
 			}
@@ -1068,14 +1061,14 @@ static void program_copt1(unsigned long *dimm_populated,
 				if (registered == 1) {
 					/* DDR2 always buffered */
 					mcopt1 |= SDRAM_MCOPT1_RDEN;
-					buf1 = TRUE;
+					buf1 = true;
 				} else {
 					if ((attribute & 0x02) == 0x00) {
 						/* buffered not supported */
-						buf1 = FALSE;
+						buf1 = false;
 					} else {
 						mcopt1 |= SDRAM_MCOPT1_RDEN;
-						buf1 = TRUE;
+						buf1 = true;
 					}
 				}
 			}
@@ -1087,11 +1080,11 @@ static void program_copt1(unsigned long *dimm_populated,
 			switch (data_width) {
 			case 72:
 			case 64:
-				dimm_64bit = TRUE;
+				dimm_64bit = true;
 				break;
 			case 40:
 			case 32:
-				dimm_32bit = TRUE;
+				dimm_32bit = true;
 				break;
 			default:
 				printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
@@ -1110,20 +1103,19 @@ static void program_copt1(unsigned long *dimm_populated,
 		}
 	}
 
-	if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
+	if ((dimm_64bit == true) && (dimm_32bit == true)) {
 		printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
 		spd_ddr_init_hang ();
-	}
-	else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
+	} else if ((dimm_64bit == true) && (dimm_32bit == false)) {
 		mcopt1 |= SDRAM_MCOPT1_DMWD_64;
-	} else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
+	} else if ((dimm_64bit == false) && (dimm_32bit == true)) {
 		mcopt1 |= SDRAM_MCOPT1_DMWD_32;
 	} else {
 		printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
 		spd_ddr_init_hang ();
 	}
 
-	if (ecc_enabled == TRUE)
+	if (ecc_enabled == true)
 		mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
 	else
 		mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
@@ -1171,14 +1163,14 @@ static void program_codt(unsigned long *dimm_populated,
 			total_rank += dimm_rank;
 			total_dimm++;
 			if ((dimm_num == 0) && (total_dimm == 1))
-				firstSlot = TRUE;
+				firstSlot = true;
 			else
-				firstSlot = FALSE;
+				firstSlot = false;
 		}
 	}
 	if (dimm_type == SDRAM_DDR2) {
 		codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
-		if ((total_dimm == 1) && (firstSlot == TRUE)) {
+		if ((total_dimm == 1) && (firstSlot == true)) {
 			if (total_rank == 1) {	/* PUUU */
 				codt |= CALC_ODT_R(0);
 				modt0 = CALC_ODT_W(0);
@@ -1193,7 +1185,7 @@ static void program_codt(unsigned long *dimm_populated,
 				modt2 = 0x00000000;
 				modt3 = 0x00000000;
 			}
-		} else if ((total_dimm == 1) && (firstSlot != TRUE)) {
+		} else if ((total_dimm == 1) && (firstSlot != true)) {
 			if (total_rank == 1) {	/* UUPU */
 				codt |= CALC_ODT_R(2);
 				modt0 = 0x00000000;
@@ -1467,26 +1459,26 @@ static void program_mode(unsigned long *dimm_populated,
 	 * the dimm modules installed.
 	 *-----------------------------------------------------------------*/
 	t_wr_ns = 0;
-	cas_2_0_available = TRUE;
-	cas_2_5_available = TRUE;
-	cas_3_0_available = TRUE;
-	cas_4_0_available = TRUE;
-	cas_5_0_available = TRUE;
+	cas_2_0_available = true;
+	cas_2_5_available = true;
+	cas_3_0_available = true;
+	cas_4_0_available = true;
+	cas_5_0_available = true;
 	max_2_0_tcyc_ns_x_100 = 10;
 	max_2_5_tcyc_ns_x_100 = 10;
 	max_3_0_tcyc_ns_x_100 = 10;
 	max_4_0_tcyc_ns_x_100 = 10;
 	max_5_0_tcyc_ns_x_100 = 10;
-	sdram_ddr1 = TRUE;
+	sdram_ddr1 = true;
 
 	/* loop through all the DIMM slots on the board */
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		/* If a dimm is installed in a particular slot ... */
 		if (dimm_populated[dimm_num] != SDRAM_NONE) {
 			if (dimm_populated[dimm_num] == SDRAM_DDR1)
-				sdram_ddr1 = TRUE;
+				sdram_ddr1 = true;
 			else
-				sdram_ddr1 = FALSE;
+				sdram_ddr1 = false;
 
 			cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
 			debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
@@ -1543,7 +1535,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_4_0_available = FALSE;
+					cas_4_0_available = false;
 				}
 
 				if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
@@ -1554,7 +1546,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_3_0_available = FALSE;
+					cas_3_0_available = false;
 				}
 
 				if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
@@ -1565,7 +1557,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_2_5_available = FALSE;
+					cas_2_5_available = false;
 				}
 
 				if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
@@ -1576,7 +1568,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_2_0_available = FALSE;
+					cas_2_0_available = false;
 				}
 			} else {
 				/*
@@ -1592,7 +1584,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_5_0_available = FALSE;
+					cas_5_0_available = false;
 				}
 
 				if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
@@ -1603,7 +1595,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_4_0_available = FALSE;
+					cas_4_0_available = false;
 				}
 
 				if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
@@ -1614,7 +1606,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_3_0_available = FALSE;
+					cas_3_0_available = false;
 				}
 			}
 		}
@@ -1636,14 +1628,17 @@ static void program_mode(unsigned long *dimm_populated,
 	debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
 	debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
 
-	if (sdram_ddr1 == TRUE) { /* DDR1 */
-		if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
+	if (sdram_ddr1 == true) { /* DDR1 */
+		if ((cas_2_0_available == true) &&
+			(sdram_freq <= cycle_2_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
 			*selected_cas = DDR_CAS_2;
-		} else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
+		} else if ((cas_2_5_available == true) &&
+			(sdram_freq <= cycle_2_5_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
 			*selected_cas = DDR_CAS_2_5;
-		} else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+		} else if ((cas_3_0_available == true) &&
+			(sdram_freq <= cycle_3_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
 			*selected_cas = DDR_CAS_3;
 		} else {
@@ -1656,13 +1651,16 @@ static void program_mode(unsigned long *dimm_populated,
 		debug("cas_3_0_available=%d\n", cas_3_0_available);
 		debug("cas_4_0_available=%d\n", cas_4_0_available);
 		debug("cas_5_0_available=%d\n", cas_5_0_available);
-		if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+		if ((cas_3_0_available == true) &&
+			(sdram_freq <= cycle_3_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
 			*selected_cas = DDR_CAS_3;
-		} else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
+		} else if ((cas_4_0_available == true) &&
+			(sdram_freq <= cycle_4_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
 			*selected_cas = DDR_CAS_4;
-		} else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
+		} else if ((cas_5_0_available == true) &&
+			(sdram_freq <= cycle_5_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
 			*selected_cas = DDR_CAS_5;
 		} else {
@@ -1677,7 +1675,7 @@ static void program_mode(unsigned long *dimm_populated,
 		}
 	}
 
-	if (sdram_ddr1 == TRUE)
+	if (sdram_ddr1 == true)
 		mmode |= SDRAM_MMODE_WR_DDR1;
 	else {
 
@@ -1851,16 +1849,16 @@ static void program_tr(unsigned long *dimm_populated,
 	t_wpc_ns = 0;
 	t_wtr_ns = 0;
 	t_rpc_ns = 0;
-	sdram_ddr1 = TRUE;
+	sdram_ddr1 = true;
 
 	/* loop through all the DIMM slots on the board */
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		/* If a dimm is installed in a particular slot ... */
 		if (dimm_populated[dimm_num] != SDRAM_NONE) {
 			if (dimm_populated[dimm_num] == SDRAM_DDR2)
-				sdram_ddr1 = TRUE;
+				sdram_ddr1 = true;
 			else
-				sdram_ddr1 = FALSE;
+				sdram_ddr1 = false;
 
 			t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
 			t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
@@ -1925,7 +1923,7 @@ static void program_tr(unsigned long *dimm_populated,
 		break;
 	}
 
-	if (sdram_ddr1 == TRUE) { /* DDR1 */
+	if (sdram_ddr1 == true) { /* DDR1 */
 		if (sdram_freq < 200000000) {
 			sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
 			sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
@@ -2548,8 +2546,8 @@ calibration_loop:
 	current_pass_length = 0;
 	current_fail_length = 0;
 	current_start = 0;
-	fail_found = FALSE;
-	pass_found = FALSE;
+	fail_found = false;
+	pass_found = false;
 
 	/*
 	 * get the delay line calibration register value
@@ -2570,8 +2568,8 @@ calibration_loop:
 		 * See if the rffd value passed.
 		 *-----------------------------------------------------------------*/
 		if (short_mem_test()) {
-			if (fail_found == TRUE) {
-				pass_found = TRUE;
+			if (fail_found == true) {
+				pass_found = true;
 				if (current_pass_length == 0)
 					current_start = rffd;
 
@@ -2589,11 +2587,10 @@ calibration_loop:
 			current_fail_length++;
 
 			if (current_fail_length >= (dly_val >> 2)) {
-				if (fail_found == FALSE) {
-					fail_found = TRUE;
-				} else if (pass_found == TRUE) {
+				if (fail_found == false)
+					fail_found = true;
+				else if (pass_found == true)
 					break;
-				}
 			}
 		}
 	}		/* for rffd */
@@ -2618,9 +2615,9 @@ calibration_loop:
 	current_pass_length = 0;
 	current_fail_length = 0;
 	current_start = 0;
-	window_found = FALSE;
-	fail_found = FALSE;
-	pass_found = FALSE;
+	window_found = false;
+	fail_found = false;
+	pass_found = false;
 
 	for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
 		mfsdram(SDRAM_RQDC, rqdc_reg);
@@ -2635,8 +2632,8 @@ calibration_loop:
 		 * See if the rffd value passed.
 		 *-----------------------------------------------------------------*/
 		if (short_mem_test()) {
-			if (fail_found == TRUE) {
-				pass_found = TRUE;
+			if (fail_found == true) {
+				pass_found = true;
 				if (current_pass_length == 0)
 					current_start = rqfd;
 
@@ -2653,10 +2650,10 @@ calibration_loop:
 			current_pass_length = 0;
 			current_fail_length++;
 
-			if (fail_found == FALSE) {
-				fail_found = TRUE;
-			} else if (pass_found == TRUE) {
-				window_found = TRUE;
+			if (fail_found == false) {
+				fail_found = true;
+			} else if (pass_found == true) {
+				window_found = true;
 				break;
 			}
 		}
@@ -2667,7 +2664,7 @@ calibration_loop:
 	/*------------------------------------------------------------------
 	 * Make sure we found the valid read passing window.  Halt if not
 	 *-----------------------------------------------------------------*/
-	if (window_found == FALSE) {
+	if (window_found == false) {
 		if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
 			putc('\b');
 			putc(slash[loopi++ % 8]);
@@ -2769,13 +2766,13 @@ static void test(void)
 	mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
 		SDRAM_MCOPT1_MCHK_NON);
 
-	window_found = FALSE;
-	begin_found[0] = FALSE;
-	end_found[0] = FALSE;
-	search_end[0] = FALSE;
-	begin_found[1] = FALSE;
-	end_found[1] = FALSE;
-	search_end[1] = FALSE;
+	window_found = false;
+	begin_found[0] = false;
+	end_found[0] = false;
+	search_end[0] = false;
+	begin_found[1] = false;
+	end_found[1] = false;
+	search_end[1] = false;
 
 	for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
 		mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
@@ -2812,32 +2809,32 @@ static void test(void)
 			 * See if the rffd value passed.
 			 *-----------------------------------------------------------------*/
 			if (i < NUMMEMTESTS) {
-				if ((end_found[dimm_num] == FALSE) &&
-				    (search_end[dimm_num] == TRUE)) {
-					end_found[dimm_num] = TRUE;
+				if ((end_found[dimm_num] == false) &&
+				    (search_end[dimm_num] == true)) {
+					end_found[dimm_num] = true;
 				}
-				if ((end_found[0] == TRUE) &&
-				    (end_found[1] == TRUE))
+				if ((end_found[0] == true) &&
+				    (end_found[1] == true))
 					break;
 			} else {
-				if (begin_found[dimm_num] == FALSE) {
-					begin_found[dimm_num] = TRUE;
-					search_end[dimm_num] = TRUE;
+				if (begin_found[dimm_num] == false) {
+					begin_found[dimm_num] = true;
+					search_end[dimm_num] = true;
 				}
 			}
 		} else {
-			begin_found[dimm_num] = TRUE;
-			end_found[dimm_num] = TRUE;
+			begin_found[dimm_num] = true;
+			end_found[dimm_num] = true;
 		}
 	}
 
-	if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
-		window_found = TRUE;
+	if ((begin_found[0] == true) && (begin_found[1] == true))
+		window_found = true;
 
 	/*------------------------------------------------------------------
 	 * Make sure we found the valid read passing window.  Halt if not
 	 *-----------------------------------------------------------------*/
-	if (window_found == FALSE) {
+	if (window_found == false) {
 		printf("ERROR: Cannot determine a common read delay for the "
 		       "DIMM(s) installed.\n");
 		spd_ddr_init_hang ();
diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
index ce769a7..3ceab32 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
@@ -53,13 +53,6 @@
 /*-----------------------------------------------------------------------------+
  * Defines
  *-----------------------------------------------------------------------------*/
-#ifndef	TRUE
-#define TRUE		1
-#endif
-#ifndef FALSE
-#define FALSE		0
-#endif
-
 #define MAXDIMMS	2
 #define MAXRANKS	2
 
@@ -279,7 +272,7 @@ static void get_spd_info(unsigned long dimm_ranks[],
 			 unsigned long num_dimm_banks)
 {
 	unsigned long dimm_num;
-	unsigned long dimm_found = FALSE;
+	unsigned long dimm_found = false;
 	unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
 	unsigned char num_of_bytes;
 	unsigned char total_size;
@@ -334,7 +327,7 @@ static void get_spd_info(unsigned long dimm_ranks[],
 				       "\n\n");
 				spd_ddr_init_hang();
 			}
-			dimm_found = TRUE;
+			dimm_found = true;
 			debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
 			      "\n", dimm_num, ranks_on_dimm);
 			if (ranks_on_dimm > max_ranks_per_dimm) {
@@ -355,7 +348,7 @@ static void get_spd_info(unsigned long dimm_ranks[],
 			debug("DIMM slot %lu: Not populated\n", dimm_num);
 		}
 	}
-	if (dimm_found == FALSE) {
+	if (dimm_found == false) {
 		printf("ERROR: No memory installed.\n");
 		printf("Install at least one DDR2 DIMM.\n\n");
 		spd_ddr_init_hang();
@@ -882,7 +875,7 @@ static void program_ddr0_22(unsigned long dimm_ranks[],
 			/* Check for ECC */
 			if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
 				  0x02)) {
-				ecc_available = FALSE;
+				ecc_available = false;
 			}
 		}
 	}
diff --git a/arch/powerpc/lib/ticks.S b/arch/powerpc/lib/ticks.S
index 1781039..63114bb 100644
--- a/arch/powerpc/lib/ticks.S
+++ b/arch/powerpc/lib/ticks.S
@@ -50,19 +50,24 @@ wait_ticks:
 	stwu	r1, -16(r1)
 	mflr	r0		/* save link register */
 	stw	r0, 20(r1)	/* Use r0 or GDB will be unhappy */
-	mr	r7, r3		/* save tick count */
+	stw	r14, 12(r1)	/* save used registers */
+	stw	r15, 8(r1)
+	mr	r14, r3		/* save tick count */
 	bl	get_ticks	/* Get start time */
 
 	/* Calculate end time */
-	addc    r7, r4, r7	/* Compute end time lower */
-	addze	r6, r3		/*     and end time upper */
+	addc    r14, r4, r14	/* Compute end time lower */
+	addze	r15, r3		/*     and end time upper */
 
 	WATCHDOG_RESET		/* Trigger watchdog, if needed */
 1:	bl	get_ticks	/* Get current time */
-	subfc	r4, r4, r7	/* Subtract current time from end time */
-	subfe.	r3, r3, r6
+	subfc	r4, r4, r14	/* Subtract current time from end time */
+	subfe.	r3, r3, r15
 	bge	1b		/* Loop until time expired */
 
-	mtlr	r0		/* restore link register */
+	lwz     r15, 8(r1)	/* restore saved registers */
+	lwz     r14, 12(r1)
+	lwz     r0, 20(r1)
 	addi	r1,r1,16
+	mtlr	r0
 	blr