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| author | Ye.Li <B37916@freescale.com> | 2015-03-23 04:56:48 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 15:03:07 +0800 |
| commit | fc806c30a55abfdfaed9f653064b600601cc9836 (patch) | |
| tree | 7c8abb1bab50cb4f48811b836788bca47690ccb5 /arch | |
| parent | e52f776b03b46fc3b3c2c16c0455a2c1e7f67238 (diff) | |
| download | u-boot-imx-fc806c30a55abfdfaed9f653064b600601cc9836.zip u-boot-imx-fc806c30a55abfdfaed9f653064b600601cc9836.tar.gz u-boot-imx-fc806c30a55abfdfaed9f653064b600601cc9836.tar.bz2 | |
MLK-10448-2 mx6: L2cache: Enable the double line fill for i.MX6DQP
Since i.MX6DQP has fixed the L2 cache issue, enable the double line
fill feature to provide better performance.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit aa8a38edb67d4d1375d10bee9bf46557369fb5c4)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2ee0ce7..507f152 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -970,6 +970,9 @@ void v7_outer_cache_enable(void) #ifndef CONFIG_MX6Q val |= 0x40800000; +#else + if (is_mx6dqp()) + val |= 0x40800000; #endif writel(val, &pl310->pl310_prefetch_ctrl); |