diff options
| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:09 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:15 -0500 |
| commit | f77329cfcf65e142ffbe930594c4d411c5d66429 (patch) | |
| tree | 3093cc769699ed9d8aea3a10bb62e0311317d9c8 /arch | |
| parent | 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 (diff) | |
| download | u-boot-imx-f77329cfcf65e142ffbe930594c4d411c5d66429.zip u-boot-imx-f77329cfcf65e142ffbe930594c4d411c5d66429.tar.gz u-boot-imx-f77329cfcf65e142ffbe930594c4d411c5d66429.tar.bz2 | |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2
Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 7 |
2 files changed, 10 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 203f53d..6c2bc34 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -85,7 +85,9 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = sysclk; sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f; + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) + & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; if (mem_pll_rat > 2) sysInfo->freqDDRBus *= mem_pll_rat; else diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 1181d2b..d0824b3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1757,6 +1757,13 @@ typedef struct ccsr_gur { u32 brrl; /* Boot release */ u8 res17[24]; u32 rcwsr[16]; /* Reset control word status */ +#ifndef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f +#else +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#endif #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 |