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authorSiarhei Siamashka <siarhei.siamashka@gmail.com>2014-08-03 05:32:41 +0300
committerHans de Goede <hdegoede@redhat.com>2014-08-12 08:42:32 +0200
commite626d2d446996b4b1cd16bf65b42c080985d8a84 (patch)
tree5fbf9ee32c38d0ca8b3a6576c0f031975659e0de /arch
parentf2577967738f923571b7156ad46ef91d9fa8d9f8 (diff)
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sunxi: dram: Respect the DDR3 reset timing requirements
The RESET pin needs to be kept low for at least 200 us according to the DDR3 spec. So just do it the right way. This issue did not cause any visible major problems earlier, because the DRAM RESET pin is usually already low after the board reset. And the time gap before reaching the sunxi u-boot DRAM initialization code appeared to be sufficient. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index dc79d1c..a632926 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -48,6 +48,11 @@ static void await_completion(u32 *reg, u32 mask)
}
}
+/*
+ * This performs the external DRAM reset by driving the RESET pin low and
+ * then high again. According to the DDR3 spec, the RESET pin needs to be
+ * kept low for at least 200 us.
+ */
static void mctl_ddr3_reset(void)
{
struct sunxi_dram_reg *dram =
@@ -64,13 +69,13 @@ static void mctl_ddr3_reset(void)
if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
- udelay(2);
+ udelay(200);
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
} else
#endif
{
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
- udelay(2);
+ udelay(200);
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
}
}