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| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2012-04-24 17:33:25 +0000 |
|---|---|---|
| committer | Heiko Schocher <hs@denx.de> | 2012-07-11 10:54:29 +0200 |
| commit | de6f604de245b19ce2e330bc63b6522af134d7ae (patch) | |
| tree | f73afbff36b87d9d48259b9b227849a6d77f990c /arch | |
| parent | 211e47549b668c7cdd8658c0413a272f0d0495d4 (diff) | |
| download | u-boot-imx-de6f604de245b19ce2e330bc63b6522af134d7ae.zip u-boot-imx-de6f604de245b19ce2e330bc63b6522af134d7ae.tar.gz u-boot-imx-de6f604de245b19ce2e330bc63b6522af134d7ae.tar.bz2 | |
mxc_i2c: specify i2c base address in config file
The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-mx31/imx-regs.h | 7 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx35/imx-regs.h | 2 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 6454acb..7ddbbd6 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -606,6 +606,13 @@ struct esdc_regs { #define UART4_BASE 0x43FB0000 #define UART5_BASE 0x43FB4000 +#define I2C1_BASE_ADDR 0x43f80000 +#define I2C1_CLK_OFFSET 26 +#define I2C2_BASE_ADDR 0x43F98000 +#define I2C2_CLK_OFFSET 28 +#define I2C3_BASE_ADDR 0x43f84000 +#define I2C3_CLK_OFFSET 30 + #define ESDCTL_SDE (1 << 31) #define ESDCTL_CMD_RW (0 << 28) #define ESDCTL_CMD_PRECHARGE (1 << 28) diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index e570ad1..3146006 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -39,7 +39,7 @@ #define MAX_BASE_ADDR 0x43F04000 #define EVTMON_BASE_ADDR 0x43F08000 #define CLKCTL_BASE_ADDR 0x43F0C000 -#define I2C_BASE_ADDR 0x43F80000 +#define I2C1_BASE_ADDR 0x43F80000 #define I2C3_BASE_ADDR 0x43F84000 #define ATA_BASE_ADDR 0x43F8C000 #define UART1_BASE 0x43F90000 |