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| author | Fabio Estevam <fabio.estevam@freescale.com> | 2011-11-09 04:15:02 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2011-11-11 11:36:58 +0100 |
| commit | ce93dc9bce15434989e01a6fc6d0124a8416b25d (patch) | |
| tree | dd39ceaf651f8c163ef6765cd674a90d16c0e618 /arch | |
| parent | 94e6dd2bc51d0384422f148675efb31c5ae1a560 (diff) | |
| download | u-boot-imx-ce93dc9bce15434989e01a6fc6d0124a8416b25d.zip u-boot-imx-ce93dc9bce15434989e01a6fc6d0124a8416b25d.tar.gz u-boot-imx-ce93dc9bce15434989e01a6fc6d0124a8416b25d.tar.bz2 | |
mx31: Use proper IO accessor for GPR register
Use proper IO accessor for GPR register.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/arm1136/mx31/generic.c | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx31/imx-regs.h | 7 |
2 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 1621e9e..167e97a 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -144,14 +144,15 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) void mx31_set_gpr(enum iomux_gp_func gp, char en) { u32 l; + struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE; - l = readl(IOMUXC_GPR); + l = readl(&iomuxc->gpr); if (en) l |= gp; else l &= ~gp; - writel(l, IOMUXC_GPR); + writel(l, &iomuxc->gpr); } void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index afdaa1c..0147920 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -98,6 +98,12 @@ struct iim_regs { u32 iim_scs3; }; +struct iomuxc_regs { + u32 unused1; + u32 unused2; + u32 gpr; +}; + struct mx3_cpu_type { u8 srev; u32 v; @@ -636,7 +642,6 @@ struct esdc_regs { #define WEIM_BASE 0xb8002000 #define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_GPR (IOMUXC_BASE + 0x8) #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) |