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authorSebastien Jan <s-jan@ti.com>2012-06-13 05:16:40 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:35 +0200
commitcc009defa4211aa58b3387b59d568cf8ea863ef4 (patch)
tree95088dc82bfd4a576d24c4b90205e3c285afe451 /arch
parentb78375a806ed04eb22b963255cfdef8df702de47 (diff)
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omap4: Use a smaller M,N couple for IVA DPLL
This reduced M,N couple corresponds to the advised value from TI HW team. Tested on 4460 Pandaboard, it also provides peripheral clocks closer to the advised values. Signed-off-by: Sebastien Jan <s-jan@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/omap4/clocks.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index c568951..1d92e66 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -146,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
- {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
+ {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */