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| author | Peng Fan <Peng.Fan@freescale.com> | 2014-12-31 11:01:38 +0800 |
|---|---|---|
| committer | Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> | 2014-12-31 14:52:32 +0530 |
| commit | b93ab2ee751a4a0231330a89e2f2f29963b434d0 (patch) | |
| tree | ff1294c78d954dbe2ffcb006bcc9dc21552eb347 /arch | |
| parent | ed0c81c654209a2af71393e8756d94c7e944646b (diff) | |
| download | u-boot-imx-b93ab2ee751a4a0231330a89e2f2f29963b434d0.zip u-boot-imx-b93ab2ee751a4a0231330a89e2f2f29963b434d0.tar.gz u-boot-imx-b93ab2ee751a4a0231330a89e2f2f29963b434d0.tar.bz2 | |
arm:mx6sx add QSPI support
Add QSPI support for mx6solox.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 50 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 12 |
3 files changed, 57 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 93a02ad..a05dca3 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -434,6 +434,56 @@ static u32 get_mmdc_ch0_clk(void) } #endif +#ifdef CONFIG_MX6SX +/* qspi_num can be from 0 - 1 */ +void enable_qspi_clk(int qspi_num) +{ + u32 reg = 0; + /* Enable QuadSPI clock */ + switch (qspi_num) { + case 0: + /* disable the clock gate */ + clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); + + /* set 50M : (50 = 396 / 2 / 4) */ + reg = readl(&imx_ccm->cscmr1); + reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | + MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK); + reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | + (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)); + writel(reg, &imx_ccm->cscmr1); + + /* enable the clock gate */ + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); + break; + case 1: + /* + * disable the clock gate + * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, + * disable both of them. + */ + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + + /* set 50M : (50 = 396 / 2 / 4) */ + reg = readl(&imx_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK); + reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3)); + writel(reg, &imx_ccm->cs2cdr); + + /*enable the clock gate*/ + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + break; + default: + break; + } +} +#endif + #ifdef CONFIG_FEC_MXC int enable_fec_anatop_clock(enum enet_freq freq) { diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 226a4cd..a6de5ee 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -67,5 +67,6 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); void enable_enet_clk(unsigned char enable); +void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5314298..c968600 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -92,10 +92,10 @@ #define AIPS3_END_ADDR 0x022FFFFF #define WEIM_ARB_BASE_ADDR 0x50000000 #define WEIM_ARB_END_ADDR 0x57FFFFFF -#define QSPI1_ARB_BASE_ADDR 0x60000000 -#define QSPI1_ARB_END_ADDR 0x6FFFFFFF -#define QSPI2_ARB_BASE_ADDR 0x70000000 -#define QSPI2_ARB_END_ADDR 0x7FFFFFFF +#define QSPI0_AMBA_BASE 0x60000000 +#define QSPI0_AMBA_END 0x6FFFFFFF +#define QSPI1_AMBA_BASE 0x70000000 +#define QSPI1_AMBA_END 0x7FFFFFFF #else #define SATA_ARB_BASE_ADDR 0x02200000 #define SATA_ARB_END_ADDR 0x02203FFF @@ -262,8 +262,8 @@ #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) #ifdef CONFIG_MX6SX #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) #else #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) |