ppc4xx: Remove IOP480 support

Since the IOP480 (PPC401/3 variant from PLX) is only used on 2
boards that are not actively maintained, lets remove support
for it completely. This way the ppc4xx code will get a bit cleaner.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Marek Vasut <marex@denx.de>

7 files changed, 2 insertions, 400 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile
index 3d62255..8da2f86 100644
--- a/arch/powerpc/cpu/ppc4xx/Makefile
+++ b/arch/powerpc/cpu/ppc4xx/Makefile
@@ -53,7 +53,6 @@ COBJS	+= ecc.o
 COBJS-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o
 COBJS	+= fdt.o
 COBJS	+= interrupts.o
-COBJS	+= iop480_uart.o
 COBJS-$(CONFIG_CMD_REGINFO) += reginfo.o
 COBJS	+= sdram.o
 COBJS	+= speed.o
diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 67f1fff..60aba8c 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -79,7 +79,7 @@ static int pci_async_enabled(void)
 #endif
 #endif /* CONFIG_PCI */
 
-#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
+#if defined(CONFIG_PCI) && \
     !defined(CONFIG_405) && !defined(CONFIG_405EX)
 int pci_arbiter_enabled(void)
 {
@@ -303,7 +303,6 @@ int checkcpu (void)
 	u32 reg;
 #endif
 
-#if !defined(CONFIG_IOP480)
 	char addstr[64] = "";
 	sys_info_t sys_info;
 	int cpu_num;
@@ -671,14 +670,6 @@ int checkcpu (void)
 	printf ("       16 kB I-Cache %d kB D-Cache",
 		((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
 #endif
-#endif /* !defined(CONFIG_IOP480) */
-
-#if defined(CONFIG_IOP480)
-	printf ("PLX IOP480 (PVR=%08x)", pvr);
-	printf (" at %s MHz:", strmhz(buf, clock));
-	printf (" %u kB I-Cache", 4);
-	printf (" %u kB D-Cache", 2);
-#endif
 
 #endif /* !defined(CONFIG_405) */
 
@@ -723,15 +714,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  */
 unsigned long get_tbclk (void)
 {
-#if !defined(CONFIG_IOP480)
 	sys_info_t  sys_info;
 
 	get_sys_info(&sys_info);
 	return (sys_info.freqProcessor);
-#else
-	return (66000000);
-#endif
-
 }
 
 
diff --git a/arch/powerpc/cpu/ppc4xx/iop480_uart.c b/arch/powerpc/cpu/ppc4xx/iop480_uart.c
deleted file mode 100644
index 9473984..0000000
--- a/arch/powerpc/cpu/ppc4xx/iop480_uart.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <watchdog.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_IOP480
-
-#define SPU_BASE         0x40000000
-
-#define spu_LineStat_rc  0x00	/* Line Status Register (Read/Clear) */
-#define spu_LineStat_w   0x04	/* Line Status Register (Set) */
-#define spu_Handshk_rc   0x08	/* Handshake Status Register (Read/Clear) */
-#define spu_Handshk_w    0x0c	/* Handshake Status Register (Set) */
-#define spu_BRateDivh    0x10	/* Baud rate divisor high */
-#define spu_BRateDivl    0x14	/* Baud rate divisor low */
-#define spu_CtlReg       0x18	/* Control Register */
-#define spu_RxCmd        0x1c	/* Rx Command Register */
-#define spu_TxCmd        0x20	/* Tx Command Register */
-#define spu_RxBuff       0x24	/* Rx data buffer */
-#define spu_TxBuff       0x24	/* Tx data buffer */
-
-/*-----------------------------------------------------------------------------+
-  | Line Status Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncLSRport1           0x40000000
-#define asyncLSRport1set        0x40000004
-#define asyncLSRDataReady             0x80
-#define asyncLSRFramingError          0x40
-#define asyncLSROverrunError          0x20
-#define asyncLSRParityError           0x10
-#define asyncLSRBreakInterrupt        0x08
-#define asyncLSRTxHoldEmpty           0x04
-#define asyncLSRTxShiftEmpty          0x02
-
-/*-----------------------------------------------------------------------------+
-  | Handshake Status Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncHSRport1           0x40000008
-#define asyncHSRport1set        0x4000000c
-#define asyncHSRDsr                   0x80
-#define asyncLSRCts                   0x40
-
-/*-----------------------------------------------------------------------------+
-  | Control Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncCRport1            0x40000018
-#define asyncCRNormal                 0x00
-#define asyncCRLoopback               0x40
-#define asyncCRAutoEcho               0x80
-#define asyncCRDtr                    0x20
-#define asyncCRRts                    0x10
-#define asyncCRWordLength7            0x00
-#define asyncCRWordLength8            0x08
-#define asyncCRParityDisable          0x00
-#define asyncCRParityEnable           0x04
-#define asyncCREvenParity             0x00
-#define asyncCROddParity              0x02
-#define asyncCRStopBitsOne            0x00
-#define asyncCRStopBitsTwo            0x01
-#define asyncCRDisableDtrRts          0x00
-
-/*-----------------------------------------------------------------------------+
-  | Receiver Command Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncRCRport1           0x4000001c
-#define asyncRCRDisable               0x00
-#define asyncRCREnable                0x80
-#define asyncRCRIntDisable            0x00
-#define asyncRCRIntEnabled            0x20
-#define asyncRCRDMACh2                0x40
-#define asyncRCRDMACh3                0x60
-#define asyncRCRErrorInt              0x10
-#define asyncRCRPauseEnable           0x08
-
-/*-----------------------------------------------------------------------------+
-  | Transmitter Command Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncTCRport1           0x40000020
-#define asyncTCRDisable               0x00
-#define asyncTCREnable                0x80
-#define asyncTCRIntDisable            0x00
-#define asyncTCRIntEnabled            0x20
-#define asyncTCRDMACh2                0x40
-#define asyncTCRDMACh3                0x60
-#define asyncTCRTxEmpty               0x10
-#define asyncTCRErrorInt              0x08
-#define asyncTCRStopPause             0x04
-#define asyncTCRBreakGen              0x02
-
-/*-----------------------------------------------------------------------------+
-  | Miscellanies defines.
-  +-----------------------------------------------------------------------------*/
-#define asyncTxBufferport1      0x40000024
-#define asyncRxBufferport1      0x40000024
-#define asyncDLABLsbport1       0x40000014
-#define asyncDLABMsbport1       0x40000010
-#define asyncXOFFchar                 0x13
-#define asyncXONchar                  0x11
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-static int iop480_serial_init(void)
-{
-	unsigned short br_reg;
-
-	br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
-	/*
-	 * Init onboard UART
-	 */
-	out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
-	out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
-	out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
-	out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08);	/* Set 8 bits, no parity and 1 stop bit */
-	out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0);	/* Enable Rx */
-	out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c);	/* Enable Tx */
-	out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff);	/* Clear Handshake */
-	in_8((u8 *)SPU_BASE + spu_RxBuff);	/* Dummy read, to clear receiver */
-
-	return (0);
-}
-
-static void iop480_serial_setbrg(void)
-{
-	unsigned short br_reg;
-
-	br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
-	out_8((u8 *)SPU_BASE + spu_BRateDivl,
-	      (br_reg & 0x00ff)); /* Set baud rate divisor... */
-	out_8((u8 *)SPU_BASE + spu_BRateDivh,
-	      ((br_reg & 0xff00) >> 8)); /* ... */
-}
-
-static void iop480_serial_putc(const char c)
-{
-	if (c == '\n')
-		serial_putc ('\r');
-
-	/* load status from handshake register */
-	if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
-		out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff);	/* Clear Handshake */
-
-	out_8((u8 *)SPU_BASE + spu_TxBuff, c);	/* Put char */
-
-	while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) {
-		if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
-			out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff);	/* Clear Handshake */
-	}
-}
-
-static void iop480_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-static int iop480_serial_getc(void)
-{
-	unsigned char status = 0;
-
-	while (1) {
-		status = in_8((u8 *)asyncLSRport1);
-		if ((status & asyncLSRDataReady) != 0x0) {
-			break;
-		}
-		if ((status & ( asyncLSRFramingError |
-				asyncLSROverrunError |
-				asyncLSRParityError  |
-				asyncLSRBreakInterrupt )) != 0) {
-			(void) out_8((u8 *)asyncLSRport1,
-				     asyncLSRFramingError |
-				     asyncLSROverrunError |
-				     asyncLSRParityError  |
-				     asyncLSRBreakInterrupt );
-		}
-	}
-	return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1));
-}
-
-static int iop480_serial_tstc(void)
-{
-	unsigned char status;
-
-	status = in_8((u8 *)asyncLSRport1);
-	if ((status & asyncLSRDataReady) != 0x0) {
-		return (1);
-	}
-	if ((status & ( asyncLSRFramingError |
-			asyncLSROverrunError |
-			asyncLSRParityError  |
-			asyncLSRBreakInterrupt )) != 0) {
-		(void) out_8((u8 *)asyncLSRport1,
-			     asyncLSRFramingError |
-			     asyncLSROverrunError |
-			     asyncLSRParityError  |
-			     asyncLSRBreakInterrupt);
-	}
-	return 0;
-}
-
-static struct serial_device iop480_serial_drv = {
-	.name	= "iop480_serial",
-	.start	= iop480_serial_init,
-	.stop	= NULL,
-	.setbrg	= iop480_serial_setbrg,
-	.putc	= iop480_serial_putc,
-	.puts	= iop480_serial_puts,
-	.getc	= iop480_serial_getc,
-	.tstc	= iop480_serial_tstc,
-};
-
-void iop480_serial_initialize(void)
-{
-	serial_register(&iop480_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &iop480_serial_drv;
-}
-#endif	/* CONFIG_IOP480 */
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 09d6671..6156ac9 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -1190,22 +1190,12 @@ void get_sys_info (sys_info_t * sysInfo)
 
 int get_clocks (void)
 {
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
-    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
-    defined(CONFIG_405EX) || defined(CONFIG_405) || \
-    defined(CONFIG_440)
 	sys_info_t sys_info;
 
 	get_sys_info (&sys_info);
 	gd->cpu_clk = sys_info.freqProcessor;
 	gd->bus_clk = sys_info.freqPLB;
 
-#endif	/* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
-
-#ifdef CONFIG_IOP480
-	gd->cpu_clk = 66000000;
-	gd->bus_clk = 66000000;
-#endif
 	return (0);
 }
 
@@ -1226,11 +1216,6 @@ ulong get_bus_freq (ulong dummy)
 
 	get_sys_info (&sys_info);
 	val = sys_info.freqPLB;
-
-#elif defined(CONFIG_IOP480)
-
-	val = 66;
-
 #else
 # error get_bus_freq() not implemented
 #endif
@@ -1238,7 +1223,6 @@ ulong get_bus_freq (ulong dummy)
 	return val;
 }
 
-#if !defined(CONFIG_IOP480)
 ulong get_OPB_freq (void)
 {
 	PPC4xx_SYS_INFO sys_info;
@@ -1247,4 +1231,3 @@ ulong get_OPB_freq (void)
 
 	return sys_info.freqOPB;
 }
-#endif
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 3b0e364..7aef43b 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -806,114 +806,6 @@ _start:
 #endif /* CONFIG_440 */
 
 /*****************************************************************************/
-#ifdef CONFIG_IOP480
-	/*----------------------------------------------------------------------- */
-	/* Set up some machine state registers. */
-	/*----------------------------------------------------------------------- */
-	addi	r0,r0,0x0000		/* initialize r0 to zero */
-	mtspr	SPRN_ESR,r0		/* clear Exception Syndrome Reg */
-	mttcr	r0			/* timer control register */
-	mtexier r0			/* disable all interrupts */
-	addis	r4,r0,0xFFFF		/* set r4 to 0xFFFFFFFF (status in the */
-	ori	r4,r4,0xFFFF		/* dbsr is cleared by setting bits to 1) */
-	mtdbsr	r4			/* clear/reset the dbsr */
-	mtexisr r4			/* clear all pending interrupts */
-	addis	r4,r0,0x8000
-	mtexier r4			/* enable critical exceptions */
-	addis	r4,r0,0x0000		/* assume 403GCX - enable core clk */
-	ori	r4,r4,0x4020		/* dbling (no harm done on GA and GC */
-	mtiocr	r4			/* since bit not used) & DRC to latch */
-					/* data bus on rising edge of CAS */
-	/*----------------------------------------------------------------------- */
-	/* Clear XER. */
-	/*----------------------------------------------------------------------- */
-	mtxer	r0
-	/*----------------------------------------------------------------------- */
-	/* Invalidate i-cache and d-cache TAG arrays. */
-	/*----------------------------------------------------------------------- */
-	addi	r3,0,1024		/* 1/4 of I-cache size, half of D-cache */
-	addi	r4,0,1024		/* 1/4 of I-cache */
-..cloop:
-	iccci	0,r3
-	iccci	r4,r3
-	dccci	0,r3
-	addic.	r3,r3,-16		/* move back one cache line */
-	bne	..cloop			/* loop back to do rest until r3 = 0 */
-
-	/* */
-	/* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
-	/* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
-	/* */
-
-	/* first copy IOP480 register base address into r3 */
-	addis	r3,0,0x5000		/* IOP480 register base address hi */
-/*	ori	r3,r3,0x0000		/  IOP480 register base address lo */
-
-#ifdef CONFIG_ADCIOP
-	/* use r4 as the working variable */
-	/* turn on CS3 (LOCCTL.7) */
-	lwz	r4,0x84(r3)		/* LOCTL is at offset 0x84 */
-	andi.	r4,r4,0xff7f		/* make bit 7 = 0 -- CS3 mode */
-	stw	r4,0x84(r3)		/* LOCTL is at offset 0x84 */
-#endif
-
-#ifdef CONFIG_DASA_SIM
-	/* use r4 as the working variable */
-	/* turn on MA17 (LOCCTL.7) */
-	lwz	r4,0x84(r3)		/* LOCTL is at offset 0x84 */
-	ori	r4,r4,0x80		/* make bit 7 = 1 -- MA17 mode */
-	stw	r4,0x84(r3)		/* LOCTL is at offset 0x84 */
-#endif
-
-	/* turn on MA16..13 (LCS0BRD.12 = 0) */
-	lwz	r4,0x100(r3)		/* LCS0BRD is at offset 0x100 */
-	andi.	r4,r4,0xefff		/* make bit 12 = 0 */
-	stw	r4,0x100(r3)		/* LCS0BRD is at offset 0x100 */
-
-	/* make sure above stores all comlete before going on */
-	sync
-
-	/* last thing, set local init status done bit (DEVINIT.31) */
-	lwz	r4,0x80(r3)		/* DEVINIT is at offset 0x80 */
-	oris	r4,r4,0x8000		/* make bit 31 = 1 */
-	stw	r4,0x80(r3)		/* DEVINIT is at offset 0x80 */
-
-	/* clear all pending interrupts and disable all interrupts */
-	li	r4,-1			/* set p1 to 0xffffffff */
-	stw	r4,0x1b0(r3)		/* clear all pending interrupts */
-	stw	r4,0x1b8(r3)		/* clear all pending interrupts */
-	li	r4,0			/* set r4 to 0 */
-	stw	r4,0x1b4(r3)		/* disable all interrupts */
-	stw	r4,0x1bc(r3)		/* disable all interrupts */
-
-	/* make sure above stores all comlete before going on */
-	sync
-
-	/* Set-up icache cacheability. */
-	lis	r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
-	ori	r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
-	mticcr	r1
-	isync
-
-	/* Set-up dcache cacheability. */
-	lis	r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
-	ori	r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
-	mtdccr	r1
-
-	addis	r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
-	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
-	li	r0, 0			/* Make room for stack frame header and */
-	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
-	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
-
-	GET_GOT			/* initialize GOT access			*/
-
-	bl	board_init_f	/* run first part of init code (from Flash)	*/
-	/* NOTREACHED - board_init_f() does not return */
-
-#endif	/* CONFIG_IOP480 */
-
-/*****************************************************************************/
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || defined(CONFIG_405)
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index e6b8f69..5f9c640 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -8,7 +8,7 @@
 #include <asm/processor.h>
 
 /* bytes per L1 cache line */
-#if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
+#if defined(CONFIG_8xx)
 #define	L1_CACHE_SHIFT	4
 #elif defined(CONFIG_PPC64BRIDGE)
 #define L1_CACHE_SHIFT	7
diff --git a/arch/powerpc/include/asm/ppc405.h b/arch/powerpc/include/asm/ppc405.h
index 14a7a37..892848a 100644
--- a/arch/powerpc/include/asm/ppc405.h
+++ b/arch/powerpc/include/asm/ppc405.h
@@ -28,11 +28,7 @@
 #define PPC_128MB_SACR_BIT(addr)	((addr) >> 27)
 #define PPC_128MB_SACR_VALUE(addr)	PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
 
-#ifndef CONFIG_IOP480
 #define CONFIG_SYS_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs */
-#else
-#define CONFIG_SYS_DCACHE_SIZE		(2 << 10)	/* For PLX IOP480(403)*/
-#endif
 
 /* DCR registers */
 #define PLB0_ACR	0x0087