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| author | Ruchika Gupta <ruchika.gupta@freescale.com> | 2014-10-15 11:39:06 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-10-16 14:17:32 -0700 |
| commit | 4ba4a095da4f7d38270ee22cc1a1ce64fa47d009 (patch) | |
| tree | c32f2a05517a9cdd335d1abd93bba716c84888f4 /arch | |
| parent | 737537ef0c9622114cf1a48208abf048df1b2005 (diff) | |
| download | u-boot-imx-4ba4a095da4f7d38270ee22cc1a1ce64fa47d009.zip u-boot-imx-4ba4a095da4f7d38270ee22cc1a1ce64fa47d009.tar.gz u-boot-imx-4ba4a095da4f7d38270ee22cc1a1ce64fa47d009.tar.bz2 | |
ls102x: configs - Add hash command in freescale LS1 platforms
Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5b..f2c9687 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -19,6 +19,8 @@ #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) @@ -66,6 +68,7 @@ #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_LE #define DCU_LAYER_MAX_NUM 16 @@ -76,6 +79,7 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #else #error SoC not defined #endif |