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authorArnout Vandecappelle (Essensium/Mind) <arnout@mind.be>2012-08-27 01:37:11 +0000
committerTom Rini <trini@ti.com>2012-09-04 17:05:38 -0700
commit4aaf06415f795098b398f728ddb1324020ebe544 (patch)
treee93094c01f82b1671b06d4896583d7172e48399c /arch
parente62b008fe341030f4a80a09b66952bba65027b70 (diff)
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OMAP3: add definition of CTRL_WKUP_CTRL register
AM/DM37x SoCs add the CTRL_WKUP_CTRL register. It contains the GPIO_IO_PWRDNZ bit, which is required to be set to enable the I/O pads of gpio_126, gpio_127 and gpio_129. Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-omap3/mux.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index 71f183d..6e92b23 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -451,6 +451,11 @@
#define CONTROL_PADCONF_GPIO128 0x0A58
#define CONTROL_PADCONF_GPIO129 0x0A5A
+/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
+ * of the extended drain cells */
+#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C)
+#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6)
+
#define MUX_VAL(OFFSET,VALUE)\
writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));