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author | Alexander Graf <agraf@suse.de> | 2014-04-11 17:09:42 +0200 |
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committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:45 -0700 |
commit | 46a346834b1857ded410f44e59da93a8793f19fc (patch) | |
tree | 6f77293c2a35dfdba88d72dc6d7f7f97c1f096be /arch | |
parent | c48e686889395ee6d33c7a7d76f8399839b699d1 (diff) | |
download | u-boot-imx-46a346834b1857ded410f44e59da93a8793f19fc.zip u-boot-imx-46a346834b1857ded410f44e59da93a8793f19fc.tar.gz u-boot-imx-46a346834b1857ded410f44e59da93a8793f19fc.tar.bz2 |
PPC: 85xx: Remove IVOR reset
There is no need to set IVORs to anything but their default values,
so let's leave them where they are.
Suggested-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
[York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile]
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fixed_ivor.S | 63 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 3 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 6 |
4 files changed, 0 insertions, 76 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 81aeadd..18366a7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -767,8 +767,6 @@ skip_l2: return 0; } -extern void setup_ivors(void); - void arch_preboot_os(void) { u32 msr; @@ -781,8 +779,6 @@ void arch_preboot_os(void) msr = mfmsr(); msr &= ~(MSR_ME|MSR_CE); mtmsr(msr); - - setup_ivors(); } #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) diff --git a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S b/arch/powerpc/cpu/mpc85xx/fixed_ivor.S deleted file mode 100644 index ebbb8c0..0000000 --- a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * Kumar Gala <kumar.gala@freescale.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* This file is intended to be included by other asm code since - * we will want to execute this on both the primary core when - * it does a bootm and the secondary core's that get released - * out of the spin table */ - -#define SET_IVOR(vector_number, vector_offset) \ - li r3,vector_offset@l; \ - mtspr SPRN_IVOR##vector_number,r3; - -#define SET_GIVOR(vector_number, vector_offset) \ - li r3,vector_offset@l; \ - mtspr SPRN_GIVOR##vector_number,r3; - - SET_IVOR(0, 0x020) /* Critical Input */ - SET_IVOR(1, 0x000) /* Machine Check */ - SET_IVOR(2, 0x060) /* Data Storage */ - SET_IVOR(3, 0x080) /* Instruction Storage */ - SET_IVOR(4, 0x0a0) /* External Input */ - SET_IVOR(5, 0x0c0) /* Alignment */ - SET_IVOR(6, 0x0e0) /* Program */ - SET_IVOR(7, 0x100) /* FP Unavailable */ - SET_IVOR(8, 0x120) /* System Call */ - SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ - SET_IVOR(10, 0x160) /* Decrementer */ - SET_IVOR(11, 0x180) /* Fixed Interval Timer */ - SET_IVOR(12, 0x1a0) /* Watchdog Timer */ - SET_IVOR(13, 0x1c0) /* Data TLB Error */ - SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ - SET_IVOR(15, 0x040) /* Debug */ - -/* e500v1 & e500v2 only */ -#ifndef CONFIG_E500MC - SET_IVOR(32, 0x200) /* SPE Unavailable */ - SET_IVOR(33, 0x220) /* Embedded FP Data */ - SET_IVOR(34, 0x240) /* Embedded FP Round */ -#endif - - SET_IVOR(35, 0x260) /* Performance monitor */ - -/* e500mc only */ -#ifdef CONFIG_E500MC - SET_IVOR(36, 0x280) /* Processor doorbell */ - SET_IVOR(37, 0x2a0) /* Processor doorbell critical */ - SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */ - SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */ - SET_IVOR(40, 0x300) /* Hypervisor system call */ - SET_IVOR(41, 0x320) /* Hypervisor Priviledge */ - - SET_GIVOR(2, 0x060) /* Guest Data Storage */ - SET_GIVOR(3, 0x080) /* Guest Instruction Storage */ - SET_GIVOR(4, 0x0a0) /* Guest External Input */ - SET_GIVOR(8, 0x120) /* Guest System Call */ - SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */ - SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */ -#endif diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index fcfba7e..a2c0ad4 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -405,9 +405,6 @@ __second_half_boot_page: bne 3b isync - /* setup IVORs to match fixed offsets */ -#include "fixed_ivor.S" - /* get the upper bits of the addr */ lwz r11,ENTRY_ADDR_UPPER(r10) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index dbbd8e5..691bd3a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1965,10 +1965,4 @@ flush_dcache: isync blr - -.globl setup_ivors -setup_ivors: - -#include "fixed_ivor.S" - blr #endif /* !MINIMAL_SPL */ |