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authorThierry Reding <thierry.reding@gmail.com>2013-10-01 17:04:45 +0200
committerTom Warren <twarren@nvidia.com>2013-12-18 10:19:48 -0700
commit4475c7752d054050ffb5e844a32ab1a6881d7aa0 (patch)
tree2596beb616c0c549ce1842bd8767f229a3dbb608 /arch
parent44de8e22ecfc0106c0aea7f39b9aa85aebf46b9c (diff)
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Tegra114: Do not program CPCON field for PLLX
PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/arm720t/tegra-common/cpu.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index aa1e04f..72c69b9 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void)
int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
u32 divp, u32 cpcon)
{
+ int chip = tegra_get_chip();
u32 reg;
/* If PLLX is already enabled, just return */
@@ -151,7 +152,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
- reg = (cpcon << PLL_CPCON_SHIFT);
+ if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
+ reg = (cpcon << PLL_CPCON_SHIFT);
+ else
+ reg = 0;
/* Set dccon to PLLX_MISC if freq > 600MHz */
if (divn > 600)