diff options
author | Graeme Russ <gruss@tss-engineering.com> | 2015-01-25 12:07:53 +1100 |
---|---|---|
committer | Stefano Babic <sbabic@denx.de> | 2015-02-10 12:48:50 +0100 |
commit | 2d6286ab7983b1fca45b7cc2d670286ec4898ffd (patch) | |
tree | 37e59db56b0fe3e2769937281e8bad21c25c9764 /arch | |
parent | 7a086037071401ee781425c382846dddfe80df68 (diff) | |
download | u-boot-imx-2d6286ab7983b1fca45b7cc2d670286ec4898ffd.zip u-boot-imx-2d6286ab7983b1fca45b7cc2d670286ec4898ffd.tar.gz u-boot-imx-2d6286ab7983b1fca45b7cc2d670286ec4898ffd.tar.bz2 |
arm: mxs: Add 'Wait for JTAG user' if booted in JTAG mode
When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)
Add a debug output and simple loop to stop execution at the completion of
the SPL initialisation as a pseudo break-point when booting in JTAG mode
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 5 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mxs/sys_proto.h | 17 |
2 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 2a5f817..d7956e5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -157,6 +157,11 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, data->boot_mode_idx = bootmode; mxs_power_wait_pswitch(); + + if (mxs_boot_modes[data->boot_mode_idx].boot_pads == MXS_BM_JTAG) { + debug("SPL: Waiting for JTAG user\n"); + asm volatile ("x: b x"); + } } /* Support aparatus */ diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 062f3de..4678723 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -74,6 +74,23 @@ static const struct mxs_pair mxs_boot_modes[] = { #endif }; +#define MXS_BM_USB 0x00 +#define MXS_BM_I2C_MASTER_3V3 0x01 +#define MXS_BM_I2C_MASTER_1V8 0x11 +#define MXS_BM_SPI2_MASTER_3V3_NOR 0x02 +#define MXS_BM_SPI2_MASTER_1V8_NOR 0x12 +#define MXS_BM_SPI3_MASTER_3V3_NOR 0x03 +#define MXS_BM_SPI3_MASTER_1V8_NOR 0x13 +#define MXS_BM_NAND_3V3 0x04 +#define MXS_BM_NAND_1V8 0x14 +#define MXS_BM_JTAG 0x06 +#define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08 +#define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18 +#define MXS_BM_SDMMC0_3V3 0x09 +#define MXS_BM_SDMMC0_1V8 0x19 +#define MXS_BM_SDMMC1_3V3 0x0a +#define MXS_BM_SDMMC1_1V8 0x1a + struct mxs_spl_data { uint8_t boot_mode_idx; uint32_t mem_dram_size; |