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authorJagannadha Sutradharudu Teki <jaganna@xilinx.com>2013-07-29 23:45:16 +0530
committerJagannadha Sutradharudu Teki <jaganna@xilinx.com>2013-08-07 01:09:47 +0530
commit1465d055f9d7a81edacf30c9d20a1b51dfcbfa8d (patch)
treef432757b21ed8001e0bbe68bea850272565a6f59 /arch
parent3488850629d2d27febe1839ea0b0f92e915c35fa (diff)
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spi: Add zynq spi controller driver
Zynq spi controller driver supports 2 buses and 3 chipselects on each bus. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-zynq/hardware.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index 25f0e3d..081624e 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -17,6 +17,8 @@
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
+#define ZYNQ_SPI_BASEADDR0 0xE0006000
+#define ZYNQ_SPI_BASEADDR1 0xE0007000
/* Reflect slcr offsets */
struct slcr_regs {