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authorBin Meng <bmeng.cn@gmail.com>2015-08-15 14:37:50 -0600
committerSimon Glass <sjg@chromium.org>2015-08-26 07:54:09 -0700
commit5fb0151697088e257e0190d414cc7b2e2793b485 (patch)
tree27236bb2d0973b0666a0ed59a29640b4b29a9fa2 /arch/x86
parent5c113ff79c601d69ce08803c7238679d8c7abd13 (diff)
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x86: baytrail: Support multiple microcode copies
Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/dts/bayleybay.dts6
-rw-r--r--arch/x86/dts/minnowmax.dts3
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 8f0e192..d646987 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -230,6 +230,12 @@
update@0 {
#include "microcode/m0230671117.dtsi"
};
+ update@1 {
+#include "microcode/m0130673322.dtsi"
+ };
+ update@2 {
+#include "microcode/m0130679901.dtsi"
+ };
};
};
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index daac24e..f4e0a35 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -256,6 +256,9 @@
update@0 {
#include "microcode/m0130673322.dtsi"
};
+ update@1 {
+#include "microcode/m0130679901.dtsi"
+ };
};
};