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author | Simon Glass <sjg@chromium.org> | 2015-01-27 22:13:39 -0700 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2015-02-06 12:07:36 -0700 |
commit | 91785f70b9b7ebfd1a2da4772a8268b36f58fa3d (patch) | |
tree | 648c8dd82f5d7f8a10b0083a631b6c8dfb56d440 /arch/x86 | |
parent | 7b02bf3c7dc74ab29e5c5f826cc0cfd141e41f2d (diff) | |
download | u-boot-imx-91785f70b9b7ebfd1a2da4772a8268b36f58fa3d.zip u-boot-imx-91785f70b9b7ebfd1a2da4772a8268b36f58fa3d.tar.gz u-boot-imx-91785f70b9b7ebfd1a2da4772a8268b36f58fa3d.tar.bz2 |
x86: mmc: Move common FSP functions into a common file
Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.
This creates a generic PCI MMC device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/cpu/queensbay/tnc.c | 27 | ||||
-rw-r--r-- | arch/x86/cpu/queensbay/tnc_pci.c | 15 | ||||
-rw-r--r-- | arch/x86/cpu/queensbay/topcliff.c | 33 | ||||
-rw-r--r-- | arch/x86/lib/fsp/Makefile | 1 | ||||
-rw-r--r-- | arch/x86/lib/fsp/fsp_common.c | 55 |
5 files changed, 59 insertions, 72 deletions
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index f9b3bfa..30ab725 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -43,30 +43,3 @@ int arch_cpu_init(void) return 0; } - -int print_cpuinfo(void) -{ - post_code(POST_CPU_INFO); - return default_print_cpuinfo(); -} - -void reset_cpu(ulong addr) -{ - /* cold reset */ - outb(0x06, PORT_RESET); -} - -void board_final_cleanup(void) -{ - u32 status; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); - status = fsp_notify(NULL, INIT_PHASE_BOOT); - if (status != FSP_SUCCESS) - debug("fail, error code %x\n", status); - else - debug("OK\n"); - - return; -} diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c index 9b0b725..6c291f9 100644 --- a/arch/x86/cpu/queensbay/tnc_pci.c +++ b/arch/x86/cpu/queensbay/tnc_pci.c @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose) hose->region_count = 4; } - -int board_pci_post_scan(struct pci_controller *hose) -{ - u32 status; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); - status = fsp_notify(NULL, INIT_PHASE_PCI); - if (status != FSP_SUCCESS) - debug("fail, error code %x\n", status); - else - debug("OK\n"); - - return 0; -} diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c index b01422a..9faf1b9 100644 --- a/arch/x86/cpu/queensbay/topcliff.c +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -5,43 +5,16 @@ */ #include <common.h> -#include <errno.h> -#include <malloc.h> -#include <pci.h> +#include <mmc.h> #include <pci_ids.h> -#include <sdhci.h> static struct pci_device_id mmc_supported[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, - { } }; int cpu_mmc_init(bd_t *bis) { - struct sdhci_host *mmc_host; - pci_dev_t devbusfn; - u32 iobase; - int ret; - int i; - - for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) { - devbusfn = pci_find_devices(mmc_supported, i); - if (devbusfn == -1) - return -ENODEV; - - mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); - if (!mmc_host) - return -ENOMEM; - - mmc_host->name = "Topcliff SDHCI"; - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); - mmc_host->ioaddr = (void *)iobase; - mmc_host->quirks = 0; - ret = add_sdhci(mmc_host, 0, 0); - if (ret) - return ret; - } - - return 0; + return pci_mmc_init("Topcliff SDHCI", mmc_supported, + ARRAY_SIZE(mmc_supported)); } diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index 3a2bac0..5b12c12 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -5,5 +5,6 @@ # obj-y += fsp_car.o +obj-y += fsp_common.o obj-y += fsp_dram.o obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c new file mode 100644 index 0000000..f668259 --- /dev/null +++ b/arch/x86/lib/fsp/fsp_common.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/post.h> +#include <asm/processor.h> +#include <asm/fsp/fsp_support.h> + +int print_cpuinfo(void) +{ + post_code(POST_CPU_INFO); + return default_print_cpuinfo(); +} + +void reset_cpu(ulong addr) +{ + /* cold reset */ + outb(0x06, PORT_RESET); +} + + +int board_pci_post_scan(struct pci_controller *hose) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); + status = fsp_notify(NULL, INIT_PHASE_PCI); + if (status != FSP_SUCCESS) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return 0; +} + +void board_final_cleanup(void) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); + status = fsp_notify(NULL, INIT_PHASE_BOOT); + if (status != FSP_SUCCESS) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return; +} |