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authorBin Meng <bmeng.cn@gmail.com>2015-02-02 22:35:28 +0800
committerSimon Glass <sjg@chromium.org>2015-02-06 12:07:41 -0700
commitafee3fb8c807e1ac9713ecb31d895008e3b5251a (patch)
tree5b282d9190037b2218fa7cb74c4ad3b1df94db4b /arch/x86
parent828d9af5eca7404ded18e0ede453f8040fd01f78 (diff)
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x86: Add basic Intel Galileo board support
New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/dts/Makefile1
-rw-r--r--arch/x86/dts/galileo.dts43
2 files changed, 44 insertions, 0 deletions
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 4e0171a..7a66133 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,5 +1,6 @@
dtb-y += chromebook_link.dtb \
crownbay.dtb \
+ galileo.dtb \
minnowmax.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
new file mode 100644
index 0000000..14a19c3
--- /dev/null
+++ b/arch/x86/dts/galileo.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "Intel Galileo";
+ compatible = "intel,galileo", "intel,quark";
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = &pciuart0;
+ };
+
+ pci {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "intel,pci";
+ device_type = "pci";
+
+ pciuart0: uart@14,5 {
+ compatible = "pci8086,0936.00",
+ "pci8086,0936",
+ "pciclass,070002",
+ "pciclass,0700",
+ "x86-uart";
+ reg = <0x0000a500 0x0 0x0 0x0 0x0
+ 0x0200a510 0x0 0x0 0x0 0x0>;
+ reg-shift = <2>;
+ clock-frequency = <44236800>;
+ current-speed = <115200>;
+ };
+ };
+
+};