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authorOndrej Kupka <ondra.cap@gmail.com>2011-09-30 21:05:11 +1100
committerGraeme Russ <graeme.russ@gmail.com>2011-11-02 20:48:30 +1100
commit7b3d5380eea55f5b2e21c592b256b7077698f766 (patch)
treed195398c12668ad2fc7b64cb8a96323cc900309a /arch/x86
parentce5207e191c59b3135303fd03b98dd2ac3701ba2 (diff)
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x86: turn off cache: set control register properly
Bits should be ORed when they are supposed to be added together Signed-off-by: Ondrej Kupka <ondra.cap@gmail.com>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/cpu/start16.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
index 3d3017a..9dabff2 100644
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@@ -50,7 +50,7 @@ board_init16_ret:
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
- orl $(X86_CR0_NW & X86_CR0_CD), %eax
+ orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd