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authorBin Meng <bmeng.cn@gmail.com>2015-09-03 05:37:27 -0700
committerSimon Glass <sjg@chromium.org>2015-09-09 07:48:03 -0600
commitb06862b9d8ea7046287ac84589210ef16a1afc0d (patch)
tree6abc4a806815e7fc77144043e1a351d4ea65d93e /arch/x86/include
parent31b5aebd5e00af84709711d8b9a60ebaf9deeed6 (diff)
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x86: quark: Add USB PHY initialization support
USB PHY needs to be properly initialized per Quark firmware writer guide, otherwise the EHCI controller on Quark SoC won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/arch-quark/quark.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h
index aad7fbe..5d81976 100644
--- a/arch/x86/include/asm/arch-quark/quark.h
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -12,6 +12,7 @@
#define MSG_PORT_HOST_BRIDGE 0x03
#define MSG_PORT_RMU 0x04
#define MSG_PORT_MEM_MGR 0x05
+#define MSG_PORT_USB_AFE 0x14
#define MSG_PORT_PCIE_AFE 0x16
#define MSG_PORT_SOC_UNIT 0x31
@@ -49,6 +50,13 @@
#define ESRAM_BLK_CTRL 0x82
#define ESRAM_BLOCK_MODE 0x10000000
+/* Port 0x14: USB2 AFE Unit Port Registers */
+
+#define USB2_GLOBAL_PORT 0x4001
+#define USB2_PLL1 0x7f02
+#define USB2_PLL2 0x7f03
+#define USB2_COMPBG 0x7f04
+
/* Port 0x16: PCIe AFE Unit Port Registers */
#define PCIE_RXPICTRL0_L0 0x2080