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authorBin Meng <bmeng.cn@gmail.com>2015-01-22 11:29:41 +0800
committerSimon Glass <sjg@chromium.org>2015-01-23 17:24:55 -0700
commit3b621ccabdccb34891bb58865a9654a09c2b7279 (patch)
tree8c9321d4657a4154867bd77d92d4d5dad851dbc3 /arch/x86/include
parent49491669065c1c718d8dc0b0ebc151b3d010c17b (diff)
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x86: Test mtrr support flag before accessing mtrr msr
On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/mtrr.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 3c11740..fda4eae 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -65,7 +65,6 @@ void mtrr_open(struct mtrr_state *state);
*
* @state: Structure from mtrr_open()
*/
-/* */
void mtrr_close(struct mtrr_state *state);
/**
@@ -76,6 +75,8 @@ void mtrr_close(struct mtrr_state *state);
* @type: Requested type (MTRR_TYPE_)
* @start: Start address
* @size: Size
+ *
+ * @return: 0 on success, non-zero on failure
*/
int mtrr_add_request(int type, uint64_t start, uint64_t size);
@@ -86,6 +87,8 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size);
* It must be called with caches disabled.
*
* @do_caches: true if caches are currently on
+ *
+ * @return: 0 on success, non-zero on failure
*/
int mtrr_commit(bool do_caches);