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authorJagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki@xilinx.com>2013-09-20 18:39:47 +0530
committerMichal Simek <michal.simek@xilinx.com>2013-11-06 09:15:12 +0100
commitec4b73f09c384007b274b38052149025e080b138 (patch)
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fpga: zynqpl: Add dcache flush support
Buffers must be cache and dma aligned. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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