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authorBin Meng <bmeng.cn@gmail.com>2016-05-25 19:19:06 -0700
committerBin Meng <bmeng.cn@gmail.com>2016-05-30 10:21:12 +0800
commit0d71511a2ae03aeb3794a0461bd8c14752438c7f (patch)
treefed5a05d1b79182ed4b223af13a5fe449350eed7 /arch/x86/include/asm
parent6523dbf7cce8d8c903346f756e0e41e46ce6d6b9 (diff)
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x86: acpi: Create a common irqlinks ASL file
Move the irqlinks.asl file currently in the BayTrail directory to a common place to be shared among all x86 platforms. As the PIRQ routing control programming interface is common to Intel chipsets, leave the common part in the common file, and move the platform specific part to the platform files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm')
-rw-r--r--arch/x86/include/asm/acpi/irqlinks.asl (renamed from arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl)33
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/lpc.asl23
2 files changed, 35 insertions, 21 deletions
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/acpi/irqlinks.asl
index 0affa23..84c1e53 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
+++ b/arch/x86/include/asm/acpi/irqlinks.asl
@@ -7,26 +7,19 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-Scope (\)
-{
- /* Intel Legacy Block */
- OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
- Field(ILBS, AnyAcc, NoLock, Preserve) {
- Offset (0x8),
- PRTA, 8,
- PRTB, 8,
- PRTC, 8,
- PRTD, 8,
- PRTE, 8,
- PRTF, 8,
- PRTG, 8,
- PRTH, 8,
- Offset (0x88),
- , 3,
- UI3E, 1,
- UI4E, 1
- }
-}
+/*
+ * Intel chipset PIRQ routing control ASL description
+ *
+ * The programming interface is common to most Intel chipsets. But the PRTx
+ * registers may be mapped to different blocks. Some chipsets map them to LPC
+ * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
+ * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
+ * Block (ILB) memory space.
+ *
+ * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
+ * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
+ * defined somewhere else in the platform's ASL files.
+ */
Device (LNKA)
{
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
index 385671c..22f0d68 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -10,6 +10,27 @@
/* Intel LPC Bus Device - 0:1f.0 */
+Scope (\)
+{
+ /* Intel Legacy Block */
+ OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Field(ILBS, AnyAcc, NoLock, Preserve) {
+ Offset (0x8),
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+ Offset (0x88),
+ , 3,
+ UI3E, 1,
+ UI4E, 1
+ }
+}
+
Device (LPCB)
{
Name(_ADR, 0x001f0000)
@@ -23,7 +44,7 @@ Device (LPCB)
Offset(0x84)
}
- #include "irqlinks.asl"
+ #include <asm/acpi/irqlinks.asl>
/* Firmware Hub */
Device (FWH)