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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-10-22 19:13:32 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2015-11-13 06:46:20 -0800 |
| commit | e5ffa4bb62b4532079ea552a804178f3955775f9 (patch) | |
| tree | f2729cf1115d2d4c13adf3242520504b44f4b4c6 /arch/x86/include/asm/arch-queensbay | |
| parent | 1eb39a509354ae3c199c739bfb2d3a0d442e2cac (diff) | |
| download | u-boot-imx-e5ffa4bb62b4532079ea552a804178f3955775f9.zip u-boot-imx-e5ffa4bb62b4532079ea552a804178f3955775f9.tar.gz u-boot-imx-e5ffa4bb62b4532079ea552a804178f3955775f9.tar.bz2 | |
x86: queensbay: Really disable IGD
According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA display controller
class in the PCI configuration space, and should also prevent
it from responding to VGA legacy memory range and I/O addresses.
However test result shows that with just VGA Disable bit set and
a PCIe graphics card connected to one of the PCIe controllers on
the E6xx, accessing the VGA legacy space still causes system hang.
After a number of attempts, it turns out besides VGA Disable bit,
the SDVO (D3:F0) device should be disabled to make it work.
To simplify, use the Function Disable register (offset 0xc4)
to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
two devices will be completely disabled (invisible in the PCI
configuration space) unless a system reset is performed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm/arch-queensbay')
| -rw-r--r-- | arch/x86/include/asm/arch-queensbay/tnc.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h index 2365394..8477d92 100644 --- a/arch/x86/include/asm/arch-queensbay/tnc.h +++ b/arch/x86/include/asm/arch-queensbay/tnc.h @@ -7,10 +7,9 @@ #ifndef _X86_ARCH_TNC_H_ #define _X86_ARCH_TNC_H_ -/* IGD Control Register */ -#define IGD_GC 0x50 -#define VGA_DISABLE 0x00020000 -#define GMS_MASK 0x00700000 +/* IGD Function Disable Register */ +#define IGD_FD 0xc4 +#define FUNC_DISABLE 0x00000001 /* Memory BAR Enable */ #define MEM_BAR_EN 0x00000001 |