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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-09-09 23:20:27 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-09-16 19:53:53 -0600 |
| commit | 554778c240385b09dc01140865fe3f5d04806456 (patch) | |
| tree | 29a2a344f00b40a7aca4c7e1d7e8e938fb2f8949 /arch/x86/include/asm/arch-quark | |
| parent | 693b5f6c71c870276f5c370254fafcb10ee43cb1 (diff) | |
| download | u-boot-imx-554778c240385b09dc01140865fe3f5d04806456.zip u-boot-imx-554778c240385b09dc01140865fe3f5d04806456.tar.gz u-boot-imx-554778c240385b09dc01140865fe3f5d04806456.tar.bz2 | |
x86: quark: Initialize thermal sensor properly
Thermal sensor on Quark SoC needs to be properly initialized per
Quark firmware writer guide, otherwise when booting Linux kernel,
it triggers system shutdown because of wrong temperature in the
thermal sensor is detected by the kernel driver (see below):
[ 5.119819] thermal_sys: Critical temperature reached(206 C),shutting down
[ 5.128997] Failed to start orderly shutdown: forcing the issue
[ 5.135495] Emergency Sync complete
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm/arch-quark')
| -rw-r--r-- | arch/x86/include/asm/arch-quark/quark.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index 338c896..f6009f6 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -42,9 +42,17 @@ /* ACPI PBLK Base Address Register */ #define PBLK_BA 0x70 +/* Control Register */ +#define RMU_CTRL 0x71 + /* SPI DMA Base Address Register */ #define SPI_DMA_BA 0x7a +/* Thermal Sensor Register */ +#define TS_MODE 0xb0 +#define TS_TEMP 0xb1 +#define TS_TRIP 0xb2 + /* Port 0x05: Memory Manager Message Port Registers */ /* eSRAM Block Page Control */ @@ -65,6 +73,12 @@ /* Port 0x31: SoC Unit Port Registers */ +/* Thermal Sensor Config */ +#define TS_CFG1 0x31 +#define TS_CFG2 0x32 +#define TS_CFG3 0x33 +#define TS_CFG4 0x34 + /* PCIe Controller Config */ #define PCIE_CFG 0x36 #define PCIE_CTLR_PRI_RST 0x00010000 |