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authorBin Meng <bmeng.cn@gmail.com>2015-07-22 01:21:11 -0700
committerSimon Glass <sjg@chromium.org>2015-07-28 10:36:24 -0600
commite7cd070da61c1dc096aa8cd45185f90f6508707b (patch)
tree2a1df3a759246765b8e09363f3f5aa55b623e15d /arch/x86/include/asm/arch-qemu
parent53832bb8d62df6c369edf3fbb6c9dd4b5ed38710 (diff)
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x86: qemu: Enable I/O APIC chip select on PIIX3
The PIIX3 chipset does not integrate an I/O APIC, instead it supports connecting to an external I/O APIC which needs to be enabled manually. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm/arch-qemu')
-rw-r--r--arch/x86/include/asm/arch-qemu/qemu.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h
index 5cbffff..8c8e4ac 100644
--- a/arch/x86/include/asm/arch-qemu/qemu.h
+++ b/arch/x86/include/asm/arch-qemu/qemu.h
@@ -13,10 +13,14 @@
#define PAM_NUM 7
#define PAM_RW 0x33
+/* X-Bus Chip Select Register */
+#define XBCS 0x4e
+#define APIC_EN (1 << 8)
+
/* IDE Timing Register */
#define IDE0_TIM 0x40
#define IDE1_TIM 0x42
-#define IDE_DECODE_EN 0x8000
+#define IDE_DECODE_EN (1 << 15)
/* I/O Ports */
#define CMOS_ADDR_PORT 0x70