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| author | Simon Glass <sjg@chromium.org> | 2016-03-11 22:06:55 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:24 +0800 |
| commit | 06d336cca284cc767a095ce40afca79b4aa0ecb0 (patch) | |
| tree | 4ffb6481ff02ed6f29d1767fd05c2d186aa3d9ff /arch/x86/include/asm/arch-ivybridge | |
| parent | 9e66506d33eac67bfa814ccba1c9ccd06bb5b107 (diff) | |
| download | u-boot-imx-06d336cca284cc767a095ce40afca79b4aa0ecb0.zip u-boot-imx-06d336cca284cc767a095ce40afca79b4aa0ecb0.tar.gz u-boot-imx-06d336cca284cc767a095ce40afca79b4aa0ecb0.tar.bz2 | |
x86: Create a common header for Intel register access
There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.
An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).
Add a new header file for these registers, and move MCH into it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm/arch-ivybridge')
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/sandybridge.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index d137d67..59b05cc 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -38,7 +38,6 @@ #define IED_SIZE 0x400000 /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE 0xfed1c000 @@ -97,8 +96,6 @@ /* * MCHBAR */ -#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg)) - #define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define BIOS_RESET_CPL 0x5da8 /* 8bit */ |