diff options
author | Simon Glass <sjg@chromium.org> | 2016-03-11 22:07:18 -0700 |
---|---|---|
committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:25 +0800 |
commit | 2f3f477b77d3a528de41e52a8ba874fd47fb6513 (patch) | |
tree | daf0f7f7207c9ff3be56fbdfba2ad3f5a9c6fb37 /arch/x86/include/asm/arch-broadwell/iomap.h | |
parent | c13dcb3dc7aeaf0a78daff0a3d28eaaa94ad1f28 (diff) | |
download | u-boot-imx-2f3f477b77d3a528de41e52a8ba874fd47fb6513.zip u-boot-imx-2f3f477b77d3a528de41e52a8ba874fd47fb6513.tar.gz u-boot-imx-2f3f477b77d3a528de41e52a8ba874fd47fb6513.tar.bz2 |
x86: Add basic support for broadwell
This adds the broadwell architecture, with the CPU driver and some useful
header files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm/arch-broadwell/iomap.h')
-rw-r--r-- | arch/x86/include/asm/arch-broadwell/iomap.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-broadwell/iomap.h b/arch/x86/include/asm/arch-broadwell/iomap.h new file mode 100644 index 0000000..431bc23 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell/iomap.h @@ -0,0 +1,53 @@ +/* + * From Coreboot soc/intel/broadwell/include/soc/iomap.h + * + * Copyright (C) 2016 Google Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __asm_arch_iomap_h +#define __asm_arch_iomap_h + +#define MCFG_BASE_ADDRESS 0xf0000000 +#define MCFG_BASE_SIZE 0x4000000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define MCH_BASE_ADDRESS 0xfed10000 +#define MCH_BASE_SIZE 0x8000 + +#define DMI_BASE_ADDRESS 0xfed18000 +#define DMI_BASE_SIZE 0x1000 + +#define EP_BASE_ADDRESS 0xfed19000 +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_ADDRESS 0xfed80000 +#define EDRAM_BASE_SIZE 0x4000 + +#define GDXC_BASE_ADDRESS 0xfed84000 +#define GDXC_BASE_SIZE 0x1000 + +#define RCBA_BASE_ADDRESS 0xfed1c000 +#define RCBA_BASE_SIZE 0x4000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define ACPI_BASE_ADDRESS 0x1000 +#define ACPI_BASE_SIZE 0x100 + +#define GPIO_BASE_ADDRESS 0x1400 +#define GPIO_BASE_SIZE 0x400 + +#define SMBUS_BASE_ADDRESS 0x0400 +#define SMBUS_BASE_SIZE 0x10 + +/* Temporary addresses used before relocation */ +#define EARLY_GTT_BAR 0xe0000000 +#define EARLY_XHCI_BAR 0xd7000000 +#define EARLY_EHCI_BAR 0xd8000000 +#define EARLY_UART_BAR 0x3f8 +#define EARLY_TEMP_MMIO 0xfed08000 + +#endif |