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authorSimon Glass <sjg@chromium.org>2014-11-14 18:18:36 -0700
committerSimon Glass <sjg@chromium.org>2014-11-25 06:34:01 -0700
commitb021e05535c3dabc07fbac2222db535d414110dc (patch)
tree5dee8ac0748dec4688cbbd63bea2059e69cc0c22 /arch/x86/dts
parent72cd085aaed511abf1ece0b406b79b90d26826af (diff)
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x86: dts: Move PCI peripherals into a pci node
These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts')
-rw-r--r--arch/x86/dts/link.dts28
1 files changed, 15 insertions, 13 deletions
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 9329916..4520db5 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -163,21 +163,23 @@
};
};
- lpc {
- compatible = "intel,lpc";
- #address-cells = <1>;
- #size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
- cros-ec@200 {
- compatible = "google,cros-ec";
- reg = <0x204 1 0x200 1 0x880 0x80>;
-
- /* This describes the flash memory within the EC */
+ pci {
+ lpc {
+ compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
- flash@8000000 {
- reg = <0x08000000 0x20000>;
- erase-value = <0xff>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
+ cros-ec@200 {
+ compatible = "google,cros-ec";
+ reg = <0x204 1 0x200 1 0x880 0x80>;
+
+ /* Describes the flash memory within the EC */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0xff>;
+ };
};
};
};