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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2014-02-05 11:28:26 +0900
committerTom Rini <trini@ti.com>2014-02-19 11:10:05 -0500
commit5ab502cb8900aee483dfba28700640672e0b060e (patch)
tree55cdefd0d3db1f47bbe0292cfbd571eed0dd76b1 /arch/x86/dts
parent6ab6b2afa091dbceb37719b8a81637a00834be19 (diff)
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dts: move device tree sources to arch/$(ARCH)/dts/
Unlike Linux Kernel, U-Boot historically had *.dts files under board/$(VENDOR)/dts/ and *.dtsi files under arch/$(ARCH)/dts/. I think arch/$(ARCH)/dts dicretory is a better location to store both *.dts and *.dtsi files. For example, before this commit, board/xilinx/dts directory had both Microblaze dts (microblaze-generic.dts) and ARM dts (zynq-*.dts), which are totally unrelated. This commit moves *.dts to arch/$(ARCH)/dts/ directories, allowing us to describe nicely mutiple DTBs generation in the next commit. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch/x86/dts')
-rw-r--r--arch/x86/dts/alex.dts24
-rw-r--r--arch/x86/dts/link.dts35
2 files changed, 59 insertions, 0 deletions
diff --git a/arch/x86/dts/alex.dts b/arch/x86/dts/alex.dts
new file mode 100644
index 0000000..2f13544
--- /dev/null
+++ b/arch/x86/dts/alex.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+/include/ "coreboot.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Google Alex";
+ compatible = "google,alex", "intel,atom-pineview";
+
+ config {
+ silent_console = <0>;
+ };
+
+ gpio: gpio {};
+
+ serial {
+ reg = <0x3f8 8>;
+ clock-frequency = <115200>;
+ };
+
+ chosen { };
+ memory { device_type = "memory"; reg = <0 0>; };
+};
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
new file mode 100644
index 0000000..4a37dac
--- /dev/null
+++ b/arch/x86/dts/link.dts
@@ -0,0 +1,35 @@
+/dts-v1/;
+
+/include/ "coreboot.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Google Link";
+ compatible = "google,link", "intel,celeron-ivybridge";
+
+ config {
+ silent_console = <0>;
+ };
+
+ gpio: gpio {};
+
+ serial {
+ reg = <0x3f8 8>;
+ clock-frequency = <115200>;
+ };
+
+ chosen { };
+ memory { device_type = "memory"; reg = <0 0>; };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich9";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "winbond,w25q64", "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ };
+ };
+};