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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-05-25 22:35:06 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 02:39:39 -0600 |
| commit | 05b98ec3468547057666dd685b2a1615298c24cc (patch) | |
| tree | f6b4914a6cc6423e573dbf059ce8b8ae057f1659 /arch/x86/dts/galileo.dts | |
| parent | 5910955f3cf685c1ca4e4abd1546fc59da55239a (diff) | |
| download | u-boot-imx-05b98ec3468547057666dd685b2a1615298c24cc.zip u-boot-imx-05b98ec3468547057666dd685b2a1615298c24cc.tar.gz u-boot-imx-05b98ec3468547057666dd685b2a1615298c24cc.tar.bz2 | |
x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/galileo.dts')
| -rw-r--r-- | arch/x86/dts/galileo.dts | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 60dbc5f..2ba081e 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -7,6 +7,7 @@ /dts-v1/; #include <dt-bindings/mrc/quark.h> +#include <dt-bindings/interrupt-router/intel-irq.h> /include/ "skeleton.dtsi" @@ -67,6 +68,27 @@ clock-frequency = <44236800>; current-speed = <115200>; }; + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xdef8>; + intel,pirq-routing = < + PCI_BDF(0, 20, 0) INTA PIRQE + PCI_BDF(0, 20, 1) INTB PIRQF + PCI_BDF(0, 20, 2) INTC PIRQG + PCI_BDF(0, 20, 3) INTD PIRQH + PCI_BDF(0, 20, 4) INTA PIRQE + PCI_BDF(0, 20, 5) INTB PIRQF + PCI_BDF(0, 20, 6) INTC PIRQG + PCI_BDF(0, 20, 7) INTD PIRQH + PCI_BDF(0, 21, 0) INTA PIRQE + PCI_BDF(0, 21, 1) INTB PIRQF + PCI_BDF(0, 21, 2) INTC PIRQG + >; + }; }; gpioa { |