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| author | Andrew Bradford <andrew.bradford@kodakalaris.com> | 2015-06-03 12:37:39 -0400 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 03:03:18 -0600 |
| commit | afbbd413a3ef8a45155fcd083814ba645b09fcc7 (patch) | |
| tree | 33e1f29fa3bcb8865a9b21926c8e0df7ffc71310 /arch/x86/cpu | |
| parent | 5c564226fc8948e435edea8eb8c5c4afbc5edef1 (diff) | |
| download | u-boot-imx-afbbd413a3ef8a45155fcd083814ba645b09fcc7.zip u-boot-imx-afbbd413a3ef8a45155fcd083814ba645b09fcc7.tar.gz u-boot-imx-afbbd413a3ef8a45155fcd083814ba645b09fcc7.tar.bz2 | |
x86: baytrail: pci region 3 is not always mapped to end of ram
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up. There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/baytrail/pci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c index 6c291f9..48409de 100644 --- a/arch/x86/cpu/baytrail/pci.c +++ b/arch/x86/cpu/baytrail/pci.c @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) pci_set_region(hose->regions + 3, 0, 0, - gd->ram_size, + gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; |