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author | Graeme Russ <graeme.russ@gmail.com> | 2011-12-27 22:46:43 +1100 |
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committer | Graeme Russ <graeme.russ@gmail.com> | 2012-01-04 22:19:01 +1100 |
commit | d653244b12dbc4a954e1bdfd04222bbbaf67329c (patch) | |
tree | 965618562edd5e8000c078cc9fe9c7d7084b72f9 /arch/x86/cpu | |
parent | 3766bb33a52217a5921c4a0a65a7281859d15bce (diff) | |
download | u-boot-imx-d653244b12dbc4a954e1bdfd04222bbbaf67329c.zip u-boot-imx-d653244b12dbc4a954e1bdfd04222bbbaf67329c.tar.gz u-boot-imx-d653244b12dbc4a954e1bdfd04222bbbaf67329c.tar.bz2 |
x86: Create weak init_cache() and default enable_caches() functions
--
Changes for v2:
- Tweaked commit title
Diffstat (limited to 'arch/x86/cpu')
-rw-r--r-- | arch/x86/cpu/cpu.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 8c3b92c..e9bb0d7 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -140,6 +140,14 @@ int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f"))); int x86_cpu_init_r(void) { + /* Initialize core interrupt and exception functionality of CPU */ + cpu_init_interrupts(); + return 0; +} +int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); + +void x86_enable_caches(void) +{ const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); /* turn on the cache and disable write through */ @@ -147,12 +155,16 @@ int x86_cpu_init_r(void) "andl %0, %%eax\n" "movl %%eax, %%cr0\n" "wbinvd\n" : : "i" (nw_cd_rst) : "eax"); +} +void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); + +int x86_init_cache(void) +{ + enable_caches(); - /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts(); return 0; } -int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); +int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { |