summaryrefslogtreecommitdiff
path: root/arch/x86/cpu
diff options
context:
space:
mode:
authorBin Meng <bmeng.cn@gmail.com>2015-02-04 16:26:09 +0800
committerSimon Glass <sjg@chromium.org>2015-02-06 12:07:44 -0700
commitb162257d4f175b59ebedd9c2db930d29317ffe16 (patch)
tree27c5fd548d015f58730eea4de8ea950445ca6c8b /arch/x86/cpu
parent20c34115d603745cf276c683168292d02056791a (diff)
downloadu-boot-imx-b162257d4f175b59ebedd9c2db930d29317ffe16.zip
u-boot-imx-b162257d4f175b59ebedd9c2db930d29317ffe16.tar.gz
u-boot-imx-b162257d4f175b59ebedd9c2db930d29317ffe16.tar.bz2
x86: quark: Initialize non-standard BARs
Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
-rw-r--r--arch/x86/cpu/quark/quark.c46
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 47ba152..cf596e4 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -9,6 +9,46 @@
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/processor.h>
+#include <asm/arch/device.h>
+#include <asm/arch/msg_port.h>
+#include <asm/arch/quark.h>
+
+static void quark_setup_bars(void)
+{
+ /* GPIO - D31:F0:R44h */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
+ CONFIG_GPIO_BASE | IO_BAR_EN);
+
+ /* ACPI PM1 Block - D31:F0:R48h */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
+ CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
+
+ /* GPE0 - D31:F0:R4Ch */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
+ CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
+
+ /* WDT - D31:F0:R84h */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
+ CONFIG_WDT_BASE | IO_BAR_EN);
+
+ /* RCBA - D31:F0:RF0h */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
+ CONFIG_RCBA_BASE | MEM_BAR_EN);
+
+ /* ACPI P Block - Msg Port 04:R70h */
+ msg_port_write(MSG_PORT_RMU, PBLK_BA,
+ CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
+
+ /* SPI DMA - Msg Port 04:R7Ah */
+ msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
+ CONFIG_SPI_DMA_BASE | IO_BAR_EN);
+
+ /* PCIe ECAM */
+ msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
+ CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
+ msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
+ CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
+}
int arch_cpu_init(void)
{
@@ -28,6 +68,12 @@ int arch_cpu_init(void)
if (ret)
return ret;
+ /*
+ * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
+ * which need be initialized with suggested values
+ */
+ quark_setup_bars();
+
return 0;
}