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authorDuncan Laurie <dlaurie@chromium.org>2012-11-03 11:41:35 +0000
committerSimon Glass <sjg@chromium.org>2012-12-06 14:30:43 -0800
commitb83058cd235acca426b1964e3aa394f7ecf16ccc (patch)
tree09678eb2189f83966096ba583029d9b4ce9d1e78 /arch/x86/cpu
parent488b8b242b72fe551dc38e33af8c7f94747610bd (diff)
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x86: Issue SMI to finalize Coreboot in final stage
This will write magic value to APMC command port which will trigger an SMI and cause coreboot to lock down the ME, chipset, and CPU. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
-rw-r--r--arch/x86/cpu/coreboot/coreboot.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index f73977f..1c8a007 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -118,5 +118,9 @@ int board_final_cleanup(void)
enable_caches();
}
+ /* Issue SMI to Coreboot to lock down ME and registers */
+ printf("Finalizing Coreboot\n");
+ outb(0xcb, 0xb2);
+
return 0;
}