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authorDuncan Laurie <dlaurie@chromium.org>2012-12-03 13:59:00 +0000
committerSimon Glass <sjg@chromium.org>2012-12-06 14:30:43 -0800
commit488b8b242b72fe551dc38e33af8c7f94747610bd (patch)
tree889cdc73a846b039daba627f50ce6d7b3594320b /arch/x86/cpu
parent300081aa68d705ce954c516751a9c03efa1fba5e (diff)
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x86: Fix MTRR clear to detect which MTRR to use
Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
-rw-r--r--arch/x86/cpu/coreboot/coreboot.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 5a4c3e5..f73977f 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -94,6 +94,8 @@ void setup_pcat_compatibility()
{
}
+#define MTRR_TYPE_WP 5
+#define MTRRcap_MSR 0xfe
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
@@ -101,11 +103,20 @@ int board_final_cleanup(void)
{
/* Un-cache the ROM so the kernel has one
* more MTRR available.
+ *
+ * Coreboot should have assigned this to the
+ * top available variable MTRR.
*/
- disable_caches();
- wrmsrl(MTRRphysBase_MSR(7), 0);
- wrmsrl(MTRRphysMask_MSR(7), 0);
- enable_caches();
+ u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
+ u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
+
+ /* Make sure this MTRR is the correct Write-Protected type */
+ if (top_type == MTRR_TYPE_WP) {
+ disable_caches();
+ wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
+ wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
+ enable_caches();
+ }
return 0;
}