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| author | Simon Glass <sjg@chromium.org> | 2014-11-06 13:20:03 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-11-21 07:24:09 +0100 |
| commit | 3c00695ee1d73ef52eadd7d4a1de9ecaab4f7be4 (patch) | |
| tree | f8df1c089d1e70f5cd158d984f12928864589897 /arch/x86/cpu/start16.S | |
| parent | 85d87328ea3d16b8e099854684166732e1954c71 (diff) | |
| download | u-boot-imx-3c00695ee1d73ef52eadd7d4a1de9ecaab4f7be4.zip u-boot-imx-3c00695ee1d73ef52eadd7d4a1de9ecaab4f7be4.tar.gz u-boot-imx-3c00695ee1d73ef52eadd7d4a1de9ecaab4f7be4.tar.bz2 | |
x86: Invalidate TLB as early as possible
We should invalidate the TLB right at the start to ensure that we don't get
false address translations even though paging is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/start16.S')
| -rw-r--r-- | arch/x86/cpu/start16.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index e718d4b..445d5a1 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -24,6 +24,9 @@ start16: /* Set the Cold Boot / Hard Reset flag */ movl $GD_FLG_COLD_BOOT, %ebx + xorl %eax, %eax + movl %eax, %cr3 /* Invalidate TLB */ + /* Turn off cache (this might require a 486-class CPU) */ movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax |